void omap3_irq_handle(void) {
/* Function called from assembly to handle interrupts */
/* get irq */
int irq = mmio_read(omap_intr.base + OMAP3_INTCPS_SIR_IRQ) & OMAP3_INTR_ACTIVEIRQ_MASK;
/* handle irq */
irq_handle(irq);
/* re-enable. this should not trigger interrupts due to current cpsr state */
mmio_write(omap_intr.base + OMAP3_INTCPS_CONTROL,OMAP3_INTR_NEWIRQAGR);
}
// =====================================================================================================================
void arch_irq_handler(struct irq_context* ctx)
{
unsigned irq = ctx->int_num - 0x20 /* pic is remapped to starts HW interrupts at 0x20 */;
int spurious = pic_is_masked(irq) && !pic_is_irq_real(irq);
if (spurious)
{
kprintf("irq: received spurious IRQ: %d\n", irq);
return;
}
irq_handle(irq, ctx);
}
static void at91sam926x_gpio_irqparse(struct int_pin *ipin, __u32 irq)
{
__u32 dwPioStat;
__u32 nPioIdx, nPioPin;
nPioIdx = irq - PIO_IRQ_OFFSET;
dwPioStat = readl(VA(PIO_BASE(nPioIdx) + PIO_ISR));
dwPioStat &= readl(VA(PIO_BASE(nPioIdx) + PIO_IMR));
// printf("%s(): stat = 0x%08x\n", __func__, dwPioStat);
for (nPioPin = 0; nPioPin < 32; nPioPin++) {
if (dwPioStat & (1 << nPioPin))
irq_handle(32 + 32 * nPioIdx + nPioPin);
}
}
void (*irq_top_handler(void))() {
uint16_t n;
// putc('!');
n = pic_irq_get_pending();
// puthex_32((GIC_DIST)->irq_active_status);
if(n >= 1020) {
return &irq_return;
}
return (irq_handle(n));
}
