void motor_pwm_emergency(void)
{
const irqstate_t irqstate = irq_primask_save();
phase_reset_all_i();
apply_phase_config();
irq_primask_restore(irqstate);
}
void motor_rtctl_emergency(void)
{
const irqstate_t irqstate = irq_primask_save();
{
motor_pwm_emergency();
_state.flags = 0;
motor_timer_cancel();
}
irq_primask_restore(irqstate);
}
static void start_timers(void)
{
const irqstate_t irqstate = irq_primask_save();
// Make sure the timers are not running
assert_always(!(TIM1->CR1 & TIM_CR1_CEN));
assert_always(!(TIM2->CR1 & TIM_CR1_CEN));
// Start synchronously
TIM1->CR2 |= TIM_CR2_MMS_0; // TIM1 is master
TIM2->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_2; // TIM2 is slave
TIM1->CR1 |= TIM_CR1_CEN; // Start all
// Make sure the timers have started now
assert_always(TIM1->CR1 & TIM_CR1_CEN);
assert_always(TIM2->CR1 & TIM_CR1_CEN);
// Configure the synchronous reset - TIM1 master, TIM2 slave
TIM1->CR2 &= ~TIM_CR2_MMS; // Master, UG bit triggers TRGO
TIM2->SMCR = TIM_SMCR_SMS_2; // Slave, TRGI triggers UG
irq_primask_restore(irqstate);
}
