static asmlinkage void __exception_irq_entry aic5_handle(struct pt_regs *regs) { struct irq_chip_generic *bgc = irq_get_domain_generic_chip(aic5_domain, 0); u32 irqnr; u32 irqstat; irqnr = irq_reg_readl(bgc, AT91_AIC5_IVR); irqstat = irq_reg_readl(bgc, AT91_AIC5_ISR); if (!irqstat) irq_reg_writel(bgc, 0, AT91_AIC5_EOICR); else handle_domain_irq(aic5_domain, irqnr, regs); }
static asmlinkage void __exception_irq_entry aic_handle(struct pt_regs *regs) { struct irq_domain_chip_generic *dgc = aic_domain->gc; struct irq_chip_generic *gc = dgc->gc[0]; u32 irqnr; u32 irqstat; irqnr = irq_reg_readl(gc, AT91_AIC_IVR); irqstat = irq_reg_readl(gc, AT91_AIC_ISR); if (!irqstat) irq_reg_writel(gc, 0, AT91_AIC_EOICR); else handle_domain_irq(aic_domain, irqnr, regs); }
static int aic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, const u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_type) { struct irq_domain_chip_generic *dgc = d->gc; struct irq_chip_generic *gc; unsigned smr; int idx; int ret; if (!dgc) return -EINVAL; ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize, out_hwirq, out_type); if (ret) return ret; idx = intspec[0] / dgc->irqs_per_chip; if (idx >= dgc->num_chips) return -EINVAL; gc = dgc->gc[idx]; irq_gc_lock(gc); smr = irq_reg_readl(gc, AT91_AIC_SMR(*out_hwirq)); ret = aic_common_set_priority(intspec[2], &smr); if (!ret) irq_reg_writel(gc, smr, AT91_AIC_SMR(*out_hwirq)); irq_gc_unlock(gc); return ret; }
static int aic5_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, const u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_type) { struct irq_domain_chip_generic *dgc = d->gc; struct irq_chip_generic *gc; unsigned smr; int ret; if (!dgc) return -EINVAL; ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize, out_hwirq, out_type); if (ret) return ret; gc = dgc->gc[0]; irq_gc_lock(gc); irq_reg_writel(*out_hwirq, gc->reg_base + AT91_AIC5_SSR); smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR); ret = aic_common_set_priority(intspec[2], &smr); if (!ret) irq_reg_writel(intspec[2] | smr, gc->reg_base + AT91_AIC5_SMR); irq_gc_unlock(gc); return ret; }
static int aic5_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, const u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_type) { struct irq_chip_generic *bgc = irq_get_domain_generic_chip(d, 0); unsigned long flags; unsigned smr; int ret; if (!bgc) return -EINVAL; ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize, out_hwirq, out_type); if (ret) return ret; irq_gc_lock_irqsave(bgc, flags); irq_reg_writel(bgc, *out_hwirq, AT91_AIC5_SSR); smr = irq_reg_readl(bgc, AT91_AIC5_SMR); ret = aic_common_set_priority(intspec[2], &smr); if (!ret) irq_reg_writel(bgc, intspec[2] | smr, AT91_AIC5_SMR); irq_gc_unlock_irqrestore(bgc, flags); return ret; }
static asmlinkage void __exception_irq_entry aic5_handle(struct pt_regs *regs) { struct irq_domain_chip_generic *dgc = aic5_domain->gc; struct irq_chip_generic *gc = dgc->gc[0]; u32 irqnr; u32 irqstat; irqnr = irq_reg_readl(gc->reg_base + AT91_AIC5_IVR); irqstat = irq_reg_readl(gc->reg_base + AT91_AIC5_ISR); irqnr = irq_find_mapping(aic5_domain, irqnr); if (!irqstat) irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR); else handle_IRQ(irqnr, regs); }
static void __exception_irq_entry digicolor_handle_irq(struct pt_regs *regs) { struct irq_domain_chip_generic *dgc = digicolor_irq_domain->gc; struct irq_chip_generic *gc = dgc->gc[0]; u32 status, hwirq; do { status = irq_reg_readl(gc, IC_INT0STATUS_LO); if (status) { hwirq = ffs(status) - 1; } else { status = irq_reg_readl(gc, IC_INT0STATUS_XLO); if (status) hwirq = ffs(status) - 1 + 32; else return; } handle_domain_irq(digicolor_irq_domain, hwirq, regs); } while (1); }
static int aic_set_type(struct irq_data *d, unsigned type) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); unsigned int smr; int ret; smr = irq_reg_readl(gc, AT91_AIC_SMR(d->hwirq)); ret = aic_common_set_type(d, type, &smr); if (ret) return ret; irq_reg_writel(gc, smr, AT91_AIC_SMR(d->hwirq)); return 0; }
static int aic5_set_type(struct irq_data *d, unsigned type) { struct irq_domain *domain = d->domain; struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); unsigned int smr; int ret; irq_gc_lock(bgc); irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR); smr = irq_reg_readl(bgc, AT91_AIC5_SMR); ret = aic_common_set_type(d, type, &smr); if (!ret) irq_reg_writel(bgc, smr, AT91_AIC5_SMR); irq_gc_unlock(bgc); return ret; }
static int aic5_set_type(struct irq_data *d, unsigned type) { struct irq_domain *domain = d->domain; struct irq_domain_chip_generic *dgc = domain->gc; struct irq_chip_generic *gc = dgc->gc[0]; unsigned int smr; int ret; irq_gc_lock(gc); irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR); smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR); ret = aic_common_set_type(d, type, &smr); if (!ret) irq_reg_writel(smr, gc->reg_base + AT91_AIC5_SMR); irq_gc_unlock(gc); return ret; }
static inline u32 ab_irqctl_readreg(struct irq_chip_generic *gc, u32 reg) { return irq_reg_readl(gc->reg_base + reg); }