int main(int argc, char *argv[])
{
ADCCON = (1 << 16) | (1 << 14) | (65 << 6);
ADCDLY = 0xffff;
wdt_init(10);
irq_request(INT_ADC, do_adc);
irq_request(INT_PENDNUP, do_updown);
irq_request(INT_WDT, do_wdt);
WAIT_DOWN;
return 0;
}
int main(int argc, char *argv[])
{
wdt_init(1000);
irq_request(26, irq_handle);
return 0;
}
int main(int argc, char *argv[])
{
if(argc != 3)
{
printf("%d", argc);
printf("\nUsage: go 0x50000000 LoadAdress FileName\n\n");
return -1;
}
hport = htons(69);
eport = htons(4321);
eth_init();
irq_disable();
GPNCON |= 2 << 14;
EINT0CON0 |= 1 << 12;
EINT0MASK &= ~(1 << 7);//设置网卡中断
irq_request(INT_EINT1, do_net);
irq_enable();
tftp_down((void *)atoi(argv[1]), argv[2]);
return 0;
}
void play_music(unsigned int start_addr, unsigned int len)
{
music_addr = start_addr;
music_len = len;
music_offset = 0;
AC_GLBCTRL |= (1 << 12) | (1 << 21);
irq_request(AC97_INT, do_music_data);
}
static void __used avr_adc_init(void)
{
mutex_init(&avr_adc_conversion_mtx);
analog_chip_init(&avr_adc_chip);
analog_syschip = &avr_adc_chip;
irq_request(ADC_COMPLETED_NUM, &avr_adc_irq, IRQ_FALLING_MASK, NULL);
/* set the prescaler to 128 */
ADCSRA |= BIT(ADPS0) | BIT(ADPS1) | BIT(ADPS2);
ADCSRA |= BIT(ADIE);
ADCSRA |= BIT(ADEN);
}
int main(void)
{
eth_init();
GPNCON |= 2 << 14;
EINT0CON0 |= 0x01 << 12;
EINT0MASK &= ~(1 << 7);
irq_request(1, do_recv);
return 0;
}
/**
* Initialize the Palacios hypervisor.
*/
static int
palacios_init(void)
{
printk(KERN_INFO "---- Initializing Palacios hypervisor support\n");
printk(KERN_INFO "cpus_weight(cpu_online_map)=0x%x\n",cpus_weight(cpu_online_map));
Init_V3(&palacios_os_hooks, NULL, cpus_weight(cpu_online_map), options);
irq_request(
IRQ1_VECTOR,
&palacios_keyboard_interrupt,
0,
"keyboard",
NULL
);
syscall_register(__NR_v3_start_guest, (syscall_ptr_t) sys_v3_start_guest);
return 0;
}
int stm32_exti_init(void)
{
int ret = 0;
ret = irq_request(EXTI0_IRQn, &stm32_exti_isr, NULL);
if (ret < 0)
goto fail;
ret = irq_request(EXTI1_IRQn, &stm32_exti_isr, NULL);
if (ret < 0)
goto fail;
ret = irq_request(EXTI2_IRQn, &stm32_exti_isr, NULL);
if (ret < 0)
goto fail;
ret = irq_request(EXTI3_IRQn, &stm32_exti_isr, NULL);
if (ret < 0)
goto fail;
ret = irq_request(EXTI4_IRQn, &stm32_exti_isr, NULL);
if (ret < 0)
goto fail;
ret = irq_request(EXTI9_5_IRQn, &stm32_exti_isr, NULL);
if (ret < 0)
goto fail;
ret = irq_request(EXTI15_10_IRQn, &stm32_exti_isr, NULL);
if (ret < 0)
goto fail;
list_initialize(&action_list);
fail:
return ret;
}
static err_t r8169_hw_init( struct netif * const netif ) {
r8169_device_t *dev = netif->state;
uint64_t paddr;
if( r8169_debug ) {
printk("Initializing r8169 hardware\n");
}
// Figure out where the r8169 registers are mapped into (physical) memory
pcicfg_bar_decode(&dev->pci_dev->cfg, 0, &dev->mem_bar);
dev->mmio_paddr = dev->mem_bar.address;
dev->mmio_vaddr = (vaddr_t) __va(dev->mmio_paddr);
if( r8169_debug ) {
printk("R8169 mmio_paddr: 0x%lx\n", dev->mmio_paddr);
printk("R8169 mmio_vaddr: 0x%lx\n", dev->mmio_vaddr);
}
// Figure out where the r8169 I/O ports are located
pcicfg_bar_decode(&dev->pci_dev->cfg, 4, &dev->io_bar);
dev->io_base = dev->io_bar.address;
dev->cur_tx = 0;
dev->cur_rx = 0;
outw(0x0000, IOADDR(dev, R8169_IMR));
/* Reset the chip */
outb(CmdReset, IOADDR(dev, R8169_CR));
outw(0xffff, IOADDR(dev, R8169_ISR));
/* Setup PHY */
PHYOUT(MII_CTRL_ANE | MII_CTRL_DM | MII_CTRL_SP_1000, MII_CTRL);
PHYOUT(MII_1000C_FULL | MII_1000C_HALF, MII_1000_CTRL);
/* Unlock Config[01234] and BMCR register writes */
outb(R9346CR_EEM_CONFIG, IOADDR(dev, R8169_9346CR));
outw(CPLUS_MULRW, IOADDR(dev, R8169_CPLUSCR));
outb(0x00, IOADDR(dev, R8169_INTRMIT));
/* Enable Tx/Rx before setting transfer thresholds */
outb(CmdRxEnb | CmdTxEnb, IOADDR(dev, R8169_CR));
/* Allocate Rx Buffers */
for( unsigned int i = 0; i < RX_RING_SIZE; i++ ) {
paddr = __pa(dev->rx_buf + (i * RX_BUF_SIZE));
dev->rx_ring[i].addr_lo = paddr & 0xfffffffful;
dev->rx_ring[i].addr_hi = paddr >> 32;
dev->rx_ring[i].opts1 = (1 << 31) | ((i==RX_RING_SIZE-1) ? (1 << 30) : 0) | RX_BUF_SIZE;
dev->rx_ring[i].opts2 = 0;
}
/* Initialize Rx */
outw(RX_BUF_SIZE, IOADDR(dev, R8169_RMS));
outl(RCR_RXFTH_UNLIM | RCR_MXDMA_1024, IOADDR(dev, R8169_RCR));
paddr = __pa(dev->rx_ring);
outl(paddr & 0xfffffffful, IOADDR(dev, R8169_RDSAR_LO));
outl(paddr >> 32, IOADDR(dev, R8169_RDSAR_HI));
/* Allocate Tx Buffers */
for( unsigned int i = 0; i < TX_RING_SIZE; i++ ) {
paddr = __pa(dev->tx_buf + (i * TX_BUF_SIZE));
dev->tx_ring[i].addr_lo = paddr & 0xfffffffful;
dev->tx_ring[i].addr_hi = paddr >> 32;
dev->tx_ring[i].opts1 = ((i==TX_RING_SIZE-1) ? (1 << 30) : 0);
dev->tx_ring[i].opts2 = 0;
}
/* Initialize Tx */
outw((TX_BUF_SIZE>>7)+1, IOADDR(dev, R8169_MTPS));
outl(TCR_MXDMA_2048 | TCR_IFG_STD, IOADDR(dev, R8169_TCR));
paddr = __pa(dev->tx_ring);
outl(paddr & 0xfffffffful, IOADDR(dev, R8169_TNPDS_LO));
outl(paddr >> 32, IOADDR(dev, R8169_TNPDS_HI));
/* Allocate Tx Buffers */
for( unsigned int i = 0; i < TX_RING_SIZE; i++ ) {
paddr = __pa(dev->tx_hi_buf + (i * TX_BUF_SIZE));
dev->tx_hi_ring[i].addr_lo = paddr & 0xfffffffful;
dev->tx_hi_ring[i].addr_hi = paddr >> 32;
dev->tx_hi_ring[i].opts1 = ((i==TX_RING_SIZE-1) ? (1 << 30) : 0);
dev->tx_hi_ring[i].opts2 = 0;
}
/* Initialize Tx */
outw((TX_BUF_SIZE>>7)+1, IOADDR(dev, R8169_MTPS));
outl(TCR_MXDMA_2048 | TCR_IFG_STD, IOADDR(dev, R8169_TCR));
paddr = __pa(dev->tx_hi_ring);
outl(paddr & 0xfffffffful, IOADDR(dev, R8169_THPDS_LO));
outl(paddr >> 32, IOADDR(dev, R8169_THPDS_HI));
/* Lock Config[01234] and BMCR register writes */
outb(R9346CR_EEM_CONFIG, IOADDR(dev, R8169_9346CR));
/* missed packet counter */
outl(0, IOADDR(dev, R8169_TCTR));
// r8169_set_rx_mode does some stuff here.
outl(inl(IOADDR(dev, R8169_RCR)) | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | AcceptAllPhys,
IOADDR(dev, R8169_RCR));
// Set Multicast address to all 1's
for( unsigned int i = 0; i < 8; i++ ) {
outb(0xff, IOADDR(dev, R8169_MAR7) + i);
}
/* Read in the MAC address */
dev->mac_addr[0] = inb(IOADDR(dev, R8169_IDR0));
dev->mac_addr[1] = inb(IOADDR(dev, R8169_IDR1));
dev->mac_addr[2] = inb(IOADDR(dev, R8169_IDR2));
dev->mac_addr[3] = inb(IOADDR(dev, R8169_IDR3));
dev->mac_addr[4] = inb(IOADDR(dev, R8169_IDR4));
dev->mac_addr[5] = inb(IOADDR(dev, R8169_IDR5));
if( r8169_debug ) {
printk("R8169 MAC Addr (%.2x:%.2x:%.2x:%.2x:%.2x:%.2x)\n",
dev->mac_addr[0],
dev->mac_addr[1],
dev->mac_addr[2],
dev->mac_addr[3],
dev->mac_addr[4],
dev->mac_addr[5]);
}
/* no early-rx interrupts */
outw(inw(IOADDR(dev, R8169_MULINT)) & 0xf000, IOADDR(dev, R8169_MULINT));
/* make sure RxTx has started */
if( !(inb(IOADDR(dev, R8169_CR)) & CmdRxEnb) || !(inb(IOADDR(dev, R8169_CR)) & CmdTxEnb) )
outb(CmdRxEnb | CmdTxEnb, IOADDR(dev, R8169_CR));
irq_request(R8169_IDTVEC, &r8169_interrupt, 0, "r8169", NULL);
/* Enable all known interrupts by setting the interrupt mask. */
outw(r8169_intr_mask, IOADDR(dev, R8169_IMR));
netif->mtu = R8169_MTU;
netif->flags = 0
| NETIF_FLAG_LINK_UP
| NETIF_FLAG_UP
| NETIF_FLAG_ETHARP
;
netif->hwaddr_len = 6;
netif->hwaddr[0] = dev->mac_addr[0];
netif->hwaddr[1] = dev->mac_addr[1];
netif->hwaddr[2] = dev->mac_addr[2];
netif->hwaddr[3] = dev->mac_addr[3];
netif->hwaddr[4] = dev->mac_addr[4];
netif->hwaddr[5] = dev->mac_addr[5];
netif->name[0] = 'e';
netif->name[1] = 'n';
netif->linkoutput = r8169_tx;
netif->output = etharp_output;
if( r8169_debug ) {
printk("r8169 initialized\n");
}
return ERR_OK;
}
