static void iseries_end_IRQ(struct irq_data *d) { unsigned int rirq = (unsigned int)irqd_to_hwirq(d); HvCallPci_eoi(REAL_IRQ_TO_BUS(rirq), REAL_IRQ_TO_SUBBUS(rirq), (REAL_IRQ_TO_IDSEL(rirq) << 4) + REAL_IRQ_TO_FUNC(rirq)); }
static int dln2_irq_set_type(struct irq_data *irqd, unsigned type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); struct dln2_gpio *dln2 = gpiochip_get_data(gc); int pin = irqd_to_hwirq(irqd); switch (type) { case IRQ_TYPE_LEVEL_HIGH: dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_HIGH; break; case IRQ_TYPE_LEVEL_LOW: dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_LOW; break; case IRQ_TYPE_EDGE_BOTH: dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE; break; case IRQ_TYPE_EDGE_RISING: dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_RISING; break; case IRQ_TYPE_EDGE_FALLING: dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_FALLING; break; default: return -EINVAL; } return 0; }
static void ics_rtas_unmask_irq(struct irq_data *d) { unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); int call_status; int server; pr_devel("xics: unmask virq %d [hw 0x%x]\n", d->irq, hw_irq); if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS) return; server = xics_get_irq_server(d->irq, d->affinity, 0); call_status = rtas_call(ibm_set_xive, 3, 1, NULL, hw_irq, server, DEFAULT_PRIORITY); if (call_status != 0) { printk(KERN_ERR "%s: ibm_set_xive irq %u server %x returned %d\n", __func__, hw_irq, server, call_status); return; } /* Now unmask the interrupt (often a no-op) */ call_status = rtas_call(ibm_int_on, 1, 1, NULL, hw_irq); if (call_status != 0) { printk(KERN_ERR "%s: ibm_int_on irq=%u returned %d\n", __func__, hw_irq, call_status); return; } }
static void bcma_gpio_irq_mask(struct irq_data *d) { struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d); int gpio = irqd_to_hwirq(d); bcma_chipco_gpio_intmask(cc, BIT(gpio), 0); }
static int lnw_irq_type(struct irq_data *d, unsigned type) { struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d); u32 gpio = irqd_to_hwirq(d); unsigned long flags; u32 value; void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER); void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER); if (gpio >= lnw->chip.ngpio) return -EINVAL; if (lnw->pdev) pm_runtime_get(&lnw->pdev->dev); spin_lock_irqsave(&lnw->lock, flags); if (type & IRQ_TYPE_EDGE_RISING) value = readl(grer) | BIT(gpio % 32); else value = readl(grer) & (~BIT(gpio % 32)); writel(value, grer); if (type & IRQ_TYPE_EDGE_FALLING) value = readl(gfer) | BIT(gpio % 32); else value = readl(gfer) & (~BIT(gpio % 32)); writel(value, gfer); spin_unlock_irqrestore(&lnw->lock, flags); if (lnw->pdev) pm_runtime_put(&lnw->pdev->dev); return 0; }
static void armada_370_xp_irq_unmask(struct irq_data *d) { #ifdef CONFIG_SMP irq_hw_number_t hwirq = irqd_to_hwirq(d); if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS) writel(hwirq, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); else writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); #else writel(irqd_to_hwirq(d), per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); #endif }
static void mpc8xxx_irq_ack(struct irq_data *d) { struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); }
static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type) { struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); unsigned int hwirq = irqd_to_hwirq(d); dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type); switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_LEVEL_HIGH: gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true, false); break; case IRQ_TYPE_LEVEL_LOW: gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true, false); break; case IRQ_TYPE_EDGE_RISING: gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, false); break; case IRQ_TYPE_EDGE_FALLING: gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false, false); break; case IRQ_TYPE_EDGE_BOTH: if (!p->config.has_both_edge_trigger) return -EINVAL; gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, true); break; default: return -EINVAL; } return 0; }
static void gpio_rcar_irq_enable(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct gpio_rcar_priv *p = gpiochip_get_data(gc); gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d))); }
/* * The interrupt controller is setup such that it doesn't work well with * the level interrupt handler in the kernel because the handler acks the * interrupt before calling the application interrupt handler. To deal with * that, we use 2 different irq chips so that different functions can be * used for level and edge type interrupts. * * IRQ Chip common (across level and edge) operations */ static void xilinx_intc_mask(struct irq_data *d) { int irq = irqd_to_hwirq(d); void * regs = irq_data_get_irq_chip_data(d); pr_debug("mask: %d\n", irq); out_be32(regs + XINTC_CIE, 1 << irq); }
static void byt_irq_shutdown(struct irq_data *d) { struct byt_gpio *vg = irq_data_get_irq_chip_data(d); byt_irq_mask(d); gpio_unlock_as_irq(&vg->chip, irqd_to_hwirq(d)); }
static void dln2_irq_mask(struct irq_data *irqd) { struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); struct dln2_gpio *dln2 = gpiochip_get_data(gc); int pin = irqd_to_hwirq(irqd); clear_bit(pin, dln2->unmasked_irqs); }
static void idu_cascade_isr(struct irq_desc *desc) { struct irq_domain *idu_domain = irq_desc_get_handler_data(desc); irq_hw_number_t core_hwirq = irqd_to_hwirq(irq_desc_get_irq_data(desc)); irq_hw_number_t idu_hwirq = core_hwirq - idu_first_hwirq; generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq)); }
static void mpc8xx_ack(struct irq_data *d) { int bit; unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d); bit = irq_nr & 0x1f; out_be32(&siu_reg->sc_sipend, 1 << (31-bit)); }
static void flipper_pic_ack(struct irq_data *d) { int irq = irqd_to_hwirq(d); void __iomem *io_base = irq_data_get_irq_chip_data(d); /* */ out_be32(io_base + FLIPPER_ICR, 1 << irq); }
static void irqc_irq_disable(struct irq_data *d) { struct irqc_priv *p = irq_data_get_irq_chip_data(d); int hw_irq = irqd_to_hwirq(d); irqc_dbg(&p->irq[hw_irq], "disable"); iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS); }
static void mpc8xxx_irq_ack(struct irq_data *d) { struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); struct gpio_chip *gc = &mpc8xxx_gc->gc; gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, gc->pin2mask(gc, irqd_to_hwirq(d))); }
static void gpio_rcar_irq_enable(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv, gpio_chip); gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d))); }
static void intc_irqpin_irq_disable(struct irq_data *d) { struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); int hw_irq = irqd_to_hwirq(d); intc_irqpin_dbg(&p->irq[hw_irq], "disable"); intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); }
static void cplds_irq_unmask(struct irq_data *d) { struct cplds *fpga = irq_data_get_irq_chip_data(d); unsigned int cplds_irq = irqd_to_hwirq(d); unsigned int bit = BIT(cplds_irq); fpga->irq_mask |= bit; writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); }
static void bcma_gpio_irq_unmask(struct irq_data *d) { struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d); int gpio = irqd_to_hwirq(d); u32 val = bcma_chipco_gpio_in(cc, BIT(gpio)); bcma_chipco_gpio_polarity(cc, BIT(gpio), val); bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio)); }
static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type) { unsigned int src = irqd_to_hwirq(d); unsigned int vold, vnew, edibit; /* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or * IRQ_TYPE_EDGE_BOTH (default). All others are IRQ_TYPE_EDGE_FALLING * or IRQ_TYPE_LEVEL_LOW (default) */ if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0) { if (flow_type == IRQ_TYPE_NONE) flow_type = IRQ_TYPE_EDGE_BOTH; if (flow_type != IRQ_TYPE_EDGE_BOTH && flow_type != IRQ_TYPE_EDGE_FALLING) goto err_sense; } else { if (flow_type == IRQ_TYPE_NONE) flow_type = IRQ_TYPE_LEVEL_LOW; if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) goto err_sense; } irqd_set_trigger_type(d, flow_type); if (flow_type & IRQ_TYPE_LEVEL_LOW) __irq_set_handler_locked(d->irq, handle_level_irq); else __irq_set_handler_locked(d->irq, handle_edge_irq); /* internal IRQ senses are LEVEL_LOW * EXT IRQ and Port C IRQ senses are programmable */ if (src >= CPM2_IRQ_EXT1 && src <= CPM2_IRQ_EXT7) edibit = (14 - (src - CPM2_IRQ_EXT1)); else if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0) edibit = (31 - (CPM2_IRQ_PORTC0 - src)); else return (flow_type & IRQ_TYPE_LEVEL_LOW) ? IRQ_SET_MASK_OK_NOCOPY : -EINVAL; vold = in_be32(&cpm2_intctl->ic_siexr); if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) vnew = vold | (1 << edibit); else vnew = vold & ~(1 << edibit); if (vold != vnew) out_be32(&cpm2_intctl->ic_siexr, vnew); return IRQ_SET_MASK_OK_NOCOPY; err_sense: pr_err("CPM2 PIC: sense type 0x%x not supported\n", flow_type); return -EINVAL; }
static void nps400_irq_unmask(struct irq_data *irqd) { unsigned int ienb; unsigned int irq = irqd_to_hwirq(irqd); ienb = read_aux_reg(AUX_IENABLE); ienb |= (1 << irq); write_aux_reg(AUX_IENABLE, ienb); }
static void ft010_irq_unmask(struct irq_data *d) { struct ft010_irq_data *f = irq_data_get_irq_chip_data(d); unsigned int mask; mask = readl(FT010_IRQ_MASK(f->base)); mask |= BIT(irqd_to_hwirq(d)); writel(mask, FT010_IRQ_MASK(f->base)); }
static void cpld_unmask_irq(struct irq_data *d) { unsigned int cpld_irq = (unsigned int)irqd_to_hwirq(d); void __iomem *pic_mask = irq_to_pic_mask(cpld_irq); out_8(pic_mask, in_8(pic_mask) & ~irq_to_pic_bit(cpld_irq)); }
static void ssb_gpio_irq_extif_unmask(struct irq_data *d) { struct ssb_bus *bus = irq_data_get_irq_chip_data(d); int gpio = irqd_to_hwirq(d); u32 val = ssb_extif_gpio_in(&bus->extif, BIT(gpio)); ssb_extif_gpio_polarity(&bus->extif, BIT(gpio), val); ssb_extif_gpio_intmask(&bus->extif, BIT(gpio), BIT(gpio)); }
static void flipper_pic_mask_and_ack(struct irq_data *d) { int irq = irqd_to_hwirq(d); void __iomem *io_base = irq_data_get_irq_chip_data(d); u32 mask = 1 << irq; clrbits32(io_base + FLIPPER_IMR, mask); /* */ out_be32(io_base + FLIPPER_ICR, mask); }
static void unmask_megamod(struct irq_data *data) { struct megamod_pic *pic = irq_data_get_irq_chip_data(data); irq_hw_number_t src = irqd_to_hwirq(data); u32 __iomem *evtmask = &pic->regs->evtmask[src / 32]; raw_spin_lock(&pic->lock); soc_writel(soc_readl(evtmask) & ~(1 << (src & 31)), evtmask); raw_spin_unlock(&pic->lock); }
static void ics_rtas_mask_irq(struct irq_data *d) { unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); pr_devel("xics: mask virq %d [hw 0x%x]\n", d->irq, hw_irq); if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS) return; ics_rtas_mask_real_irq(hw_irq); }
static void ftgpio_gpio_unmask_irq(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct ftgpio_gpio *g = gpiochip_get_data(gc); u32 val; val = readl(g->base + GPIO_INT_EN); val |= BIT(irqd_to_hwirq(d)); writel(val, g->base + GPIO_INT_EN); }