static void release_secondary_early_hpen(size_t pos) { uint32_t *p_entry = bckreg_address(BCKR_CORE1_BRANCH_ADDRESS); uint32_t *p_magic = bckreg_address(BCKR_CORE1_MAGIC_NUMBER); *p_entry = TEE_LOAD_ADDR; *p_magic = BOOT_API_A7_CORE1_MAGIC_NUMBER; dmb(); isb(); itr_raise_sgi(GIC_SEC_SGI_0, BIT(pos)); }
static void release_secondary_early_hpen(size_t __unused pos) { /* Need to send SIG#0 over Group0 after individual core 1 reset */ raise_sgi0_as_secure(); udelay(20); io_write32(stm32mp_bkpreg(BCKR_CORE1_BRANCH_ADDRESS), TEE_LOAD_ADDR); io_write32(stm32mp_bkpreg(BCKR_CORE1_MAGIC_NUMBER), BOOT_API_A7_CORE1_MAGIC_NUMBER); dsb_ishst(); itr_raise_sgi(GIC_SEC_SGI_0, TARGET_CPU1_GIC_MASK); }