/****************************************************************************** * Waits for the EEPROM to finish the current command. * * hw - Struct containing variables accessed by shared code * * The command is done when the EEPROM's data out pin goes high. * * Returns: * true: EEPROM data pin is high before timeout. * false: Time expired. *****************************************************************************/ static bool ixgb_wait_eeprom_command(struct ixgb_hw *hw) { u32 eecd_reg; u32 i; /* Toggle the CS line. This in effect tells to EEPROM to actually execute * the command in question. */ ixgb_standby_eeprom(hw); /* Now read DO repeatedly until is high (equal to '1'). The EEPROM will * signal that the command has been completed by raising the DO signal. * If DO does not go high in 10 milliseconds, then error out. */ for (i = 0; i < 200; i++) { eecd_reg = IXGB_READ_REG(hw, EECD); if (eecd_reg & IXGB_EECD_DO) return true; udelay(50); } ASSERT(0); return false; }
/****************************************************************************** * Writes a 16 bit word to a given offset in the EEPROM. * * hw - Struct containing variables accessed by shared code * reg - offset within the EEPROM to be written to * data - 16 bit word to be written to the EEPROM * * If ixgb_update_eeprom_checksum is not called after this function, the * EEPROM will most likely contain an invalid checksum. * *****************************************************************************/ void ixgb_write_eeprom(struct ixgb_hw *hw, u16 offset, u16 data) { struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; /* Prepare the EEPROM for writing */ ixgb_setup_eeprom(hw); /* Send the 9-bit EWEN (write enable) command to the EEPROM (5-bit opcode * plus 4-bit dummy). This puts the EEPROM into write/erase mode. */ ixgb_shift_out_bits(hw, EEPROM_EWEN_OPCODE, 5); ixgb_shift_out_bits(hw, 0, 4); /* Prepare the EEPROM */ ixgb_standby_eeprom(hw); /* Send the Write command (3-bit opcode + 6-bit addr) */ ixgb_shift_out_bits(hw, EEPROM_WRITE_OPCODE, 3); ixgb_shift_out_bits(hw, offset, 6); /* Send the data */ ixgb_shift_out_bits(hw, data, 16); ixgb_wait_eeprom_command(hw); /* Recover from write */ ixgb_standby_eeprom(hw); /* Send the 9-bit EWDS (write disable) command to the EEPROM (5-bit * opcode plus 4-bit dummy). This takes the EEPROM out of write/erase * mode. */ ixgb_shift_out_bits(hw, EEPROM_EWDS_OPCODE, 5); ixgb_shift_out_bits(hw, 0, 4); /* Done with writing */ ixgb_cleanup_eeprom(hw); /* clear the init_ctrl_reg_1 to signify that the cache is invalidated */ ee_map->init_ctrl_reg_1 = cpu_to_le16(EEPROM_ICW1_SIGNATURE_CLEAR); return; }
/****************************************************************************** * Writes a 16 bit word to a given offset in the EEPROM. * * hw - Struct containing variables accessed by shared code * reg - offset within the EEPROM to be written to * data - 16 bit word to be writen to the EEPROM * * If ixgb_update_eeprom_checksum is not called after this function, the * EEPROM will most likely contain an invalid checksum. * *****************************************************************************/ void ixgb_write_eeprom(struct ixgb_hw *hw, uint16_t offset, uint16_t data) { /* Prepare the EEPROM for writing */ ixgb_setup_eeprom(hw); /* Send the 9-bit EWEN (write enable) command to the EEPROM (5-bit opcode * plus 4-bit dummy). This puts the EEPROM into write/erase mode. */ ixgb_shift_out_bits(hw, EEPROM_EWEN_OPCODE, 5); ixgb_shift_out_bits(hw, 0, 4); /* Prepare the EEPROM */ ixgb_standby_eeprom(hw); /* Send the Write command (3-bit opcode + 6-bit addr) */ ixgb_shift_out_bits(hw, EEPROM_WRITE_OPCODE, 3); ixgb_shift_out_bits(hw, offset, 6); /* Send the data */ ixgb_shift_out_bits(hw, data, 16); ixgb_wait_eeprom_command(hw); /* Recover from write */ ixgb_standby_eeprom(hw); /* Send the 9-bit EWDS (write disable) command to the EEPROM (5-bit * opcode plus 4-bit dummy). This takes the EEPROM out of write/erase * mode. */ ixgb_shift_out_bits(hw, EEPROM_EWDS_OPCODE, 5); ixgb_shift_out_bits(hw, 0, 4); /* Done with writing */ ixgb_cleanup_eeprom(hw); return; }
/****************************************************************************** * Reads a 16 bit word from the EEPROM. * * hw - Struct containing variables accessed by shared code * offset - offset of 16 bit word in the EEPROM to read * * Returns: * The 16-bit value read from the eeprom *****************************************************************************/ uint16_t ixgb_read_eeprom(struct ixgb_hw *hw, uint16_t offset) { uint16_t data; /* Prepare the EEPROM for reading */ ixgb_setup_eeprom(hw); /* Send the READ command (opcode + addr) */ ixgb_shift_out_bits(hw, EEPROM_READ_OPCODE, 3); /* * We have a 64 word EEPROM, there are 6 address bits */ ixgb_shift_out_bits(hw, offset, 6); /* Read the data */ data = ixgb_shift_in_bits(hw); /* End this read operation */ ixgb_standby_eeprom(hw); return (data); }