void
ka410_conf()
{
struct vs_cpu *ka410_cpu;
ka410_cpu = (struct vs_cpu *)vax_map_physmem(VS_REGS, 1);
switch (vax_cputype) {
case VAX_TYP_UV2:
ka410_cpu->vc_410mser = 1;
printf("cpu: KA410\n");
break;
case VAX_TYP_CVAX:
printf("cpu: KA41/42\n");
ka410_cpu->vc_vdcorg = 0; /* XXX */
ka410_cpu->vc_parctl = PARCTL_CPEN | PARCTL_DPEN ;
printf("cpu: Enabling primary cache, ");
mtpr(KA420_CADR_S2E|KA420_CADR_S1E|KA420_CADR_ISE|KA420_CADR_DSE,
PR_CADR);
if (vax_confdata & KA420_CFG_CACHPR) {
l2cache = (void *)vax_map_physmem(KA420_CH2_BASE,
(KA420_CH2_SIZE / VAX_NBPG));
cacr = (void *)vax_map_physmem(KA420_CACR, 1);
printf("secondary cache\n");
ka41_cache_enable();
} else
printf("no secondary cache present\n");
}
/* Done with ka410_cpu - release it */
vax_unmap_physmem((vaddr_t)ka410_cpu, 1);
/*
* Setup parameters necessary to read time from clock chip.
*/
clk_adrshift = 1; /* Addressed at long's... */
clk_tweak = 2; /* ...and shift two */
clk_page = (short *)vax_map_physmem(KA420_WAT_BASE, 1);
}
void
ka410_conf(void)
{
struct cpu_info * const ci = curcpu();
struct vs_cpu *ka410_cpu;
ka410_cpu = (struct vs_cpu *)vax_map_physmem(VS_REGS, 1);
switch (vax_cputype) {
case VAX_TYP_UV2:
ka410_cpu->vc_410mser = 1;
ci->ci_cpustr = "KA410, UV2";
break;
case VAX_TYP_CVAX:
ka410_cpu->vc_vdcorg = 0; /* XXX */
ka410_cpu->vc_parctl = PARCTL_CPEN | PARCTL_DPEN ;
mtpr(KA420_CADR_S2E|KA420_CADR_S1E|KA420_CADR_ISE|KA420_CADR_DSE, PR_CADR);
if (vax_confdata & KA420_CFG_CACHPR) {
l2cache = (void *)vax_map_physmem(KA420_CH2_BASE,
(KA420_CH2_SIZE / VAX_NBPG));
cacr = (void *)vax_map_physmem(KA420_CACR, 1);
ka41_cache_enable();
ci->ci_cpustr =
"KA420, CVAX, 1KB L1 cache, 64KB L2 cache";
} else {
ci->ci_cpustr = "KA420, CVAX, 1KB L1 cache";
}
}
/* Done with ka410_cpu - release it */
vax_unmap_physmem((vaddr_t)ka410_cpu, 1);
/*
* Setup parameters necessary to read time from clock chip.
*/
clk_adrshift = 1; /* Addressed at long's... */
clk_tweak = 2; /* ...and shift two */
clk_page = (short *)vax_map_physmem(KA420_WAT_BASE, 1);
}
