void ksz8051Tick(NetInterface *interface)
{
uint16_t value;
bool_t linkState;
//No external interrupt line driver?
if(interface->extIntDriver == NULL)
{
//Read basic status register
value = ksz8051ReadPhyReg(interface, KSZ8051_PHY_REG_BMSR);
//Retrieve current link state
linkState = (value & BMSR_LINK_STATUS) ? TRUE : FALSE;
//Link up event?
if(linkState && !interface->linkState)
{
//Set event flag
interface->phyEvent = TRUE;
//Notify the TCP/IP stack of the event
osSetEvent(&netEvent);
}
//Link down event?
else if(!linkState && interface->linkState)
{
//Set event flag
interface->phyEvent = TRUE;
//Notify the TCP/IP stack of the event
osSetEvent(&netEvent);
}
}
}
void ksz8051Tick(NetInterface *interface)
{
//No external interrupt line driver?
if(interface->extIntDriver == NULL)
{
uint16_t value;
bool_t linkState;
//Read basic status register
value = ksz8051ReadPhyReg(interface, KSZ8051_PHY_REG_BMSR);
//Retrieve current link state
linkState = (value & BMSR_LINK_STATUS) ? TRUE : FALSE;
//Link up event?
if(linkState && !interface->linkState)
{
//A PHY event is pending...
interface->phyEvent = TRUE;
//Notify the user that the link state has changed
osSetEvent(&interface->nicRxEvent);
}
//Link down event?
else if(!linkState && interface->linkState)
{
//A PHY event is pending...
interface->phyEvent = TRUE;
//Notify the user that the link state has changed
osSetEvent(&interface->nicRxEvent);
}
}
}
error_t ksz8051Init(NetInterface *interface)
{
//Debug message
TRACE_INFO("Initializing KSZ8051...\r\n");
//Initialize external interrupt line driver
if(interface->extIntDriver != NULL)
interface->extIntDriver->init();
//Reset PHY transceiver
ksz8051WritePhyReg(interface, KSZ8051_PHY_REG_BMCR, BMCR_RESET);
//Wait for the reset to complete
while(ksz8051ReadPhyReg(interface, KSZ8051_PHY_REG_BMCR) & BMCR_RESET);
//Dump PHY registers for debugging purpose
ksz8051DumpPhyReg(interface);
//The PHY will generate interrupts when link status changes are detected
ksz8051WritePhyReg(interface, KSZ8051_PHY_REG_ICSR, ICSR_LINK_DOWN_IE | ICSR_LINK_UP_IE);
//Force the TCP/IP stack to poll the link state at startup
interface->phyEvent = TRUE;
//Notify the TCP/IP stack of the event
osSetEvent(&netEvent);
//Successful initialization
return NO_ERROR;
}
error_t ksz8051Init(NetInterface *interface)
{
GPIO_InitTypeDef GPIO_InitStructure;
EXTI_InitTypeDef EXTI_InitStructure;
NVIC_InitTypeDef NVIC_InitStructure;
//Debug message
TRACE_INFO("Initializing KSZ8051...\r\n");
//Enable GPIOB clock
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
//Enable SYSCFG clock
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
//Configure PB2 pin as an input
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_Init(GPIOB, &GPIO_InitStructure);
//Connect EXTI Line2 to PB2 pin
SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOB, EXTI_PinSource2);
//Configure EXTI Line2
EXTI_InitStructure.EXTI_Line = EXTI_Line2;
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_Init(&EXTI_InitStructure);
//Enable EXTI2 interrupts
NVIC_InitStructure.NVIC_IRQChannel = EXTI2_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 15;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 15;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
//Reset PHY transceiver
ksz8051WritePhyReg(interface, KSZ8051_PHY_REG_BMCR, BMCR_RESET);
//Wait for the reset to complete
while(ksz8051ReadPhyReg(interface, KSZ8051_PHY_REG_BMCR) & BMCR_RESET);
//Dump PHY registers for debugging purpose
ksz8051DumpPhyReg(interface);
//The PHY will generate interrupts when link status changes are detected
ksz8051WritePhyReg(interface, KSZ8051_PHY_REG_ICSR, ICSR_LINK_DOWN_IE | ICSR_LINK_UP_IE);
//Successful initialization
return NO_ERROR;
}
void ksz8051DumpPhyReg(NetInterface *interface)
{
uint8_t i;
//Loop through PHY registers
for(i = 0; i < 32; i++)
{
//Display current PHY register
TRACE_DEBUG("%02" PRIu8 ": 0x%04" PRIX16 "\r\n", i, ksz8051ReadPhyReg(interface, i));
}
//Terminate with a line feed
TRACE_DEBUG("\r\n");
}
void ksz8051EventHandler(NetInterface *interface)
{
uint16_t value;
//Read status register to acknowledge the interrupt
value = ksz8051ReadPhyReg(interface, KSZ8051_PHY_REG_ICSR);
//Link status change?
if(value & (ICSR_LINK_DOWN_IF | ICSR_LINK_UP_IF))
{
//Any link failure condition is latched in the BMSR register... Reading
//the register twice will always return the actual link status
value = ksz8051ReadPhyReg(interface, KSZ8051_PHY_REG_BMSR);
value = ksz8051ReadPhyReg(interface, KSZ8051_PHY_REG_BMSR);
//Link is up?
if(value & BMSR_LINK_STATUS)
{
//Read PHY control register
value = ksz8051ReadPhyReg(interface, KSZ8051_PHY_REG_PHYCON1);
//Check current operation mode
switch(value & PHYCON1_OP_MODE_MASK)
{
//10BASE-T
case PHYCON1_OP_MODE_10BT:
interface->linkSpeed = NIC_LINK_SPEED_10MBPS;
interface->duplexMode = NIC_HALF_DUPLEX_MODE;
break;
//10BASE-T full-duplex
case PHYCON1_OP_MODE_10BT_FD:
interface->linkSpeed = NIC_LINK_SPEED_10MBPS;
interface->duplexMode = NIC_FULL_DUPLEX_MODE;
break;
//100BASE-TX
case PHYCON1_OP_MODE_100BTX:
interface->linkSpeed = NIC_LINK_SPEED_100MBPS;
interface->duplexMode = NIC_HALF_DUPLEX_MODE;
break;
//100BASE-TX full-duplex
case PHYCON1_OP_MODE_100BTX_FD:
interface->linkSpeed = NIC_LINK_SPEED_100MBPS;
interface->duplexMode = NIC_FULL_DUPLEX_MODE;
break;
//Unknown operation mode
default:
//Debug message
TRACE_WARNING("Invalid Duplex mode\r\n");
break;
}
//Update link state
interface->linkState = TRUE;
//Adjust MAC configuration parameters for proper operation
interface->nicDriver->updateMacConfig(interface);
}
else
{
//Update link state
interface->linkState = FALSE;
}
//Process link state change event
nicNotifyLinkChange(interface);
}
}
bool_t ksz8051EventHandler(NetInterface *interface)
{
uint16_t value;
//Read status register to acknowledge the interrupt
value = ksz8051ReadPhyReg(interface, KSZ8051_PHY_REG_ICSR);
//Link status change?
if(value & (ICSR_LINK_DOWN_IF | ICSR_LINK_UP_IF))
{
//Read basic status register
value = ksz8051ReadPhyReg(interface, KSZ8051_PHY_REG_BMSR);
//Link is up?
if(value & BMSR_LINK_STATUS)
{
//Read PHY control register
value = ksz8051ReadPhyReg(interface, KSZ8051_PHY_REG_PHYCON1);
//Check current operation mode
switch(value & PHYCON1_OP_MODE_MASK)
{
//10BASE-T
case PHYCON1_OP_MODE_10BT:
interface->speed100 = FALSE;
interface->fullDuplex = FALSE;
break;
//10BASE-T full-duplex
case PHYCON1_OP_MODE_10BT_FD:
interface->speed100 = FALSE;
interface->fullDuplex = TRUE;
break;
//100BASE-TX
case PHYCON1_OP_MODE_100BTX:
interface->speed100 = TRUE;
interface->fullDuplex = FALSE;
break;
//100BASE-TX full-duplex
case PHYCON1_OP_MODE_100BTX_FD:
interface->speed100 = TRUE;
interface->fullDuplex = TRUE;
break;
//Unknown operation mode
default:
//Debug message
TRACE_WARNING("Invalid Duplex mode\r\n");
break;
}
//Update link state
interface->linkState = TRUE;
//Display link state
TRACE_INFO("Link is up (%s)...\r\n", interface->name);
//Display actual speed and duplex mode
TRACE_INFO("%s %s\r\n",
interface->speed100 ? "100BASE-TX" : "10BASE-T",
interface->fullDuplex ? "Full-Duplex" : "Half-Duplex");
}
else
{
//Update link state
interface->linkState = FALSE;
//Display link state
TRACE_INFO("Link is down (%s)...\r\n", interface->name);
}
//Notify the user that the link state has changed
return TRUE;
}
else
{
//No link state change...
return FALSE;
}
}
error_t ksz8051Init(NetInterface *interface)
{
//SAM4E-EK evaluation board?
#if defined(USE_SAM4E_EK)
volatile uint32_t status;
//Debug message
TRACE_INFO("Initializing KSZ8051...\r\n");
//Enable PIO peripheral clock
PMC->PMC_PCER0 = (1 << ID_PIOD);
//Enable pull-up resistor on PHY IRQ pin
PIOD->PIO_PUER = PIO_PD28;
//Configure the corresponding pin as an input
PIOD->PIO_ODR = PIO_PD28;
PIOD->PIO_PER = PIO_PD28;
//Enable interrupts-on-change
PIOD->PIO_IDR = 0xFFFFFFFF;
PIOD->PIO_IER = PIO_PD28;
//Reset PHY transceiver by asserting NRST pin
//RSTC->RSTC_MR = RSTC_MR_KEY(0xA5) | RSTC_MR_ERSTL(4);
//RSTC->RSTC_CR = RSTC_CR_KEY(0xA5) | RSTC_CR_EXTRST;
//Wait for the reset to complete
//while(!(RSTC->RSTC_SR & RSTC_SR_NRSTL));
//Delay before accessing PHY transceiver
sleep(10);
//Read PIO ISR register to clear any pending interrupt
status = PIOD->PIO_ISR;
//Set priority grouping (2 bits for pre-emption priority, 2 bits for subpriority)
NVIC_SetPriorityGrouping(5);
//Configure PIOD interrupt priority
NVIC_SetPriority(PIOD_IRQn, NVIC_EncodePriority(5, 2, 0));
#else
GPIO_InitTypeDef GPIO_InitStructure;
EXTI_InitTypeDef EXTI_InitStructure;
//Debug message
TRACE_INFO("Initializing KSZ8051...\r\n");
//Enable GPIOB clock
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
//Enable SYSCFG clock
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
//Configure PB2 pin as an input
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_Init(GPIOB, &GPIO_InitStructure);
//Connect EXTI Line2 to PB2 pin
SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOB, EXTI_PinSource2);
//Configure EXTI Line2
EXTI_InitStructure.EXTI_Line = EXTI_Line2;
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_Init(&EXTI_InitStructure);
//Set priority grouping (2 bits for pre-emption priority, 2 bits for subpriority)
NVIC_SetPriorityGrouping(5);
//Configure EXTI2 interrupt priority
NVIC_SetPriority(EXTI2_IRQn, NVIC_EncodePriority(5, 2, 0));
#endif
//Reset PHY transceiver
ksz8051WritePhyReg(interface, KSZ8051_PHY_REG_BMCR, BMCR_RESET);
//Wait for the reset to complete
while(ksz8051ReadPhyReg(interface, KSZ8051_PHY_REG_BMCR) & BMCR_RESET);
//Dump PHY registers for debugging purpose
ksz8051DumpPhyReg(interface);
//The PHY will generate interrupts when link status changes are detected
ksz8051WritePhyReg(interface, KSZ8051_PHY_REG_ICSR, ICSR_LINK_DOWN_IE | ICSR_LINK_UP_IE);
//Successful initialization
return NO_ERROR;
}
