int mx6_rgmii_rework(struct phy_device *phydev)
{
/*
* Bug: Apparently uDoo does not works with Gigabit switches...
* Limiting speed to 10/100Mbps, and setting master mode, seems to
* be the only way to have a successfull PHY auto negotiation.
* How to fix: Understand why Linux kernel do not have this issue.
*/
phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
/* control data pad skew - devaddr = 0x02, register = 0x04 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
/* rx data pad skew - devaddr = 0x02, register = 0x05 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
/* tx data pad skew - devaddr = 0x02, register = 0x05 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
return 0;
}
static int ksz9031_config_init(struct phy_device *phydev)
{
u16 val;
/* control data pad skew - devaddr = 0x02, register = 0x04 */
val = (0x0 << MII_KSZ9031_EXT_RGMII_RX_DV_SHIFT)
| (0x7 << MII_KSZ9031_EXT_RGMII_TX_EN_SHIFT);
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC, val);
/* rx data pad skew - devaddr = 0x02, register = 0x05 */
val = (0x0 << MII_KSZ90x1_EXT_RGMII_RX3_SHIFT)
| (0x0 << MII_KSZ90x1_EXT_RGMII_RX2_SHIFT)
| (0x0 << MII_KSZ90x1_EXT_RGMII_RX1_SHIFT)
| (0x0 << MII_KSZ90x1_EXT_RGMII_RX0_SHIFT);
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC, val);
/* tx data pad skew - devaddr = 0x02, register = 0x06 */
val = (0x7 << MII_KSZ90x1_EXT_RGMII_TX3_SHIFT)
| (0x7 << MII_KSZ90x1_EXT_RGMII_TX2_SHIFT)
| (0x7 << MII_KSZ90x1_EXT_RGMII_TX1_SHIFT)
| (0x7 << MII_KSZ90x1_EXT_RGMII_TX0_SHIFT);
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC, val);
/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
val = (0x1F << MII_KSZ9031_EXT_RGMII_GTX_CLK_SHIFT)
| (0x0E << MII_KSZ9031_EXT_RGMII_RX_CLK_SHIFT);
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC, val);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
/*
* optimized pad skew values depends on CPU variant on the TQMa6x module:
* i.MX6Q/D or i.MX6DL/S
*/
#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q)
#define MBA6X_KSZ9031_CTRL_SKEW 0x0032
#define MBA6X_KSZ9031_CLK_SKEW 0x03ff
#define MBA6X_KSZ9031_RX_SKEW 0x3333
#define MBA6X_KSZ9031_TX_SKEW 0x2036
#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#define MBA6X_KSZ9031_CTRL_SKEW 0x0030
#define MBA6X_KSZ9031_CLK_SKEW 0x03ff
#define MBA6X_KSZ9031_RX_SKEW 0x3333
#define MBA6X_KSZ9031_TX_SKEW 0x2052
#else
#error
#endif
/* min rx/tx ctrl delay */
ksz9031_phy_extended_write(phydev, 2,
MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
MBA6X_KSZ9031_CTRL_SKEW);
/* min rx delay */
ksz9031_phy_extended_write(phydev, 2,
MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
MBA6X_KSZ9031_RX_SKEW);
/* max tx delay */
ksz9031_phy_extended_write(phydev, 2,
MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
MBA6X_KSZ9031_TX_SKEW);
/* rx/tx clk skew */
ksz9031_phy_extended_write(phydev, 2,
MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
MBA6X_KSZ9031_CLK_SKEW);
phydev->drv->config(phydev);
return 0;
}
int mx6_rgmii_rework(struct phy_device *phydev)
{
/* control data pad skew - devaddr = 0x02, register = 0x04 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
/* rx data pad skew - devaddr = 0x02, register = 0x05 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
/* tx data pad skew - devaddr = 0x02, register = 0x05 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
return 0;
}
static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
int devaddr, int regnum, u16 val)
{
return ksz9031_phy_extended_write(phydev, devaddr, regnum,
MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
};
