void up_addregion(void)
{
#ifndef CONFIG_STM32_CCMEXCLUDE
#if defined(CONFIG_NUTTX_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the STM32F20xxx/STM32F40xxx CCM SRAM heap */
stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END-SRAM2_START);
#endif
/* Add the STM32F20xxx/STM32F40xxx CCM SRAM user heap region. */
kumm_addregion((FAR void*)SRAM2_START, SRAM2_END-SRAM2_START);
#endif
#ifdef CONFIG_STM32_FSMC_SRAM
#if defined(CONFIG_NUTTX_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the FSMC SRAM user heap memory */
stm32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
#endif
/* Add the external FSMC SRAM user heap region. */
kumm_addregion((FAR void*)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
#endif
}
void up_addregion(void)
{
/* Banks 0 and 1 are each 16Kb. If both are present, they occupy a
* contiguous 32Kb memory region.
*
* If Ethernet is enabled, it will take some or all of bank 0 for packet
* buffering and descriptor tables; If USB host is enabled, it will take
* some or all of bank 1 for descriptor memory. The complex conditional
* compilation above should boil this all down to a very simple check
* here:
*
* Is any memory available in AHB SRAM for the heap?
*/
#ifdef LPC17_AHB_HEAPBASE
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Yes.. allow user-mode access to the AHB SRAM user heap memory */
lpc17_mpu_uheap((uintptr_t)LPC17_AHB_HEAPBASE, LPC17_AHB_HEAPSIZE);
#endif
/* Add the AHB SRAM user heap region. */
kumm_addregion((FAR void*)LPC17_AHB_HEAPBASE, LPC17_AHB_HEAPSIZE);
#endif
}
void up_addregion(void)
{
int region_cnt;
char *mem_start = CONFIG_RAMx_START;
char *mem_size = CONFIG_RAMx_SIZE;
for (region_cnt = 0; region_cnt < CONFIG_MM_REGIONS - 1; region_cnt++) {
if (!*mem_start || !*mem_size) {
dbg("Fail to add %dth heap region\n", region_cnt + 1);
break;
}
kumm_addregion((void *)strtol(mem_start, &mem_start, 16), (size_t)strtol(mem_size, &mem_size, 0));
if (*mem_start == ',') {
mem_start++;
}
if (*mem_size == ',') {
mem_size++;
}
}
}
void up_addregion(void)
{
kumm_addregion((FAR void*)CC3200_SRAM1_BASE, CC3200_SRAM1_SIZE);
}
void up_addregion(void)
{
/* The SAM3U also have SRAM1 and NFCSRAM, We will add these as regions
* the first two additional memory regions if we have them.
*/
#ifdef HAVE_SRAM1_REGION
/* Allow user access to the heap memory */
sam_mpu_uheap(SAM_INTSRAM1_BASE, SAM34_SRAM1_SIZE);
/* Add the region */
kumm_addregion((FAR void*)SAM_INTSRAM1_BASE, SAM34_SRAM1_SIZE);
#endif /* HAVE_SRAM1_REGION */
#ifdef HAVE_NFCSRAM_REGION
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
/* In the 3X/3A family I note that clocking must appled to the SMC module
* in order for the NFCS SRAM to be functional. I don't recall such an
* issue with the 3U.
*/
sam_smc_enableclk();
#endif
/* Allow user access to the heap memory */
sam_mpu_uheap(SAM_NFCSRAM_BASE, SAM34_NFCSRAM_SIZE);
/* Add the region */
kumm_addregion((FAR void*)SAM_NFCSRAM_BASE, SAM34_NFCSRAM_SIZE);
#endif /* HAVE_NFCSRAM_REGION */
#ifdef HAVE_EXTSRAM0_REGION
/* Allow user access to the heap memory */
sam_mpu_uheap(SAM_EXTCS0_BASE, CONFIG_SAM34_EXTSRAM0SIZE);
/* Add the region */
kumm_addregion((FAR void*)SAM_EXTCS0_BASE, CONFIG_SAM34_EXTSRAM0SIZE);
#endif /* HAVE_EXTSRAM0_REGION */
#ifdef HAVE_EXTSRAM1_REGION
/* Allow user access to the heap memory */
sam_mpu_uheap(SAM_EXTCS1_BASE, CONFIG_SAM34_EXTSRAM1SIZE);
/* Add the region */
kumm_addregion((FAR void*)SAM_EXTCS1_BASE, CONFIG_SAM34_EXTSRAM1SIZE);
#endif /* HAVE_EXTSRAM0_REGION */
#ifdef HAVE_EXTSRAM2_REGION
/* Allow user access to the heap memory */
sam_mpu_uheap(SAM_EXTCS2_BASE, CONFIG_SAM34_EXTSRAM2SIZE);
/* Add the region */
kumm_addregion((FAR void*)SAM_EXTCS2_BASE, CONFIG_SAM34_EXTSRAM2SIZE);
#endif /* HAVE_EXTSRAM0_REGION */
#ifdef HAVE_EXTSRAM3_REGION
/* Allow user access to the heap memory */
sam_mpu_uheap(SAM_EXTCS3_BASE, CONFIG_SAM34_EXTSRAM3SIZE);
/* Add the region */
kumm_addregion((FAR void*)SAM_EXTCS3_BASE, CONFIG_SAM34_EXTSRAM3SIZE);
#endif /* HAVE_EXTSRAM0_REGION */
}
