int board_early_init_f(void)
{
u32 tmp;
kirkwood_mpp_conf(kwmpp_config);
/*
* The FLASH_GPIO_PIN switches between using a
* NAND or a SPI FLASH. Set this pin on start
* to NAND mode.
*/
tmp = readl(KW_GPIO0_BASE);
writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
tmp = readl(KW_GPIO0_BASE + 4);
writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
#if defined(CONFIG_SOFT_I2C)
/* init the GPIO for I2C Bitbang driver */
kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0);
kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0);
#endif
#if defined(CONFIG_SYS_EEPROM_WREN)
kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
#endif
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
/*
* The KM_FLASH_GPIO_PIN switches between using a
* NAND or a SPI FLASH. Set this pin on start
* to NAND mode.
*/
kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
#if defined(CONFIG_SOFT_I2C)
/*
* Reinit the GPIO for I2C Bitbang driver so that the now
* available gpio framework is consistent. The calls to
* direction output in are not necessary, they are already done in
* board_early_init_f
*/
kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
#endif
#if defined(CONFIG_SYS_EEPROM_WREN)
kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
#endif
#if defined(CONFIG_KM_FPGA_CONFIG)
trigger_fpga_config();
#endif
return 0;
}
int board_init(void)
{
u32 tmp;
kirkwood_mpp_conf(kwmpp_config);
/*
* The FLASH_GPIO_PIN switches between using a
* NAND or a SPI FLASH. Set this pin on start
* to NAND mode.
*/
tmp = readl(KW_GPIO0_BASE);
writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
tmp = readl(KW_GPIO0_BASE + 4);
writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
printf("KM: setting NAND mode\n");
/*
* arch number of board
*/
gd->bd->bi_arch_number = MACH_TYPE_SUEN3;
/* address of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
#if defined(CONFIG_SOFT_I2C)
/* init the GPIO for I2C Bitbang driver */
kw_gpio_set_valid(SUEN3_SDA_PIN, 1);
kw_gpio_set_valid(SUEN3_SCL_PIN, 1);
kw_gpio_direction_output(SUEN3_SDA_PIN, 0);
kw_gpio_direction_output(SUEN3_SCL_PIN, 0);
#endif
#if defined(CONFIG_SYS_EEPROM_WREN)
kw_gpio_set_valid(SUEN3_ENV_WP, 38);
kw_gpio_direction_output(SUEN3_ENV_WP, 1);
#endif
return 0;
}
int trigger_fpga_config(void)
{
int ret = 0;
/* if the FPGA is already configured, we do not want to
* reconfigure it */
skip = 0;
if (fpga_done()) {
printf("PCIe FPGA config: skipped\n");
skip = 1;
return 0;
}
if (check_boco2()) {
/* we have a BOCO2, this has to be triggered here */
/* make sure the FPGA_can access the EEPROM */
ret = boco_clear_bits(SPI_REG, CFG_EEPROM);
if (ret)
return ret;
/* trigger the config start */
ret = boco_clear_bits(SPI_REG, FPGA_PROG | FPGA_INIT_B);
if (ret)
return ret;
/* small delay for the pulse */
udelay(10);
/* up signal for pulse end */
ret = boco_set_bits(SPI_REG, FPGA_PROG);
if (ret)
return ret;
/* finally, raise INIT_B to remove the config delay */
ret = boco_set_bits(SPI_REG, FPGA_INIT_B);
if (ret)
return ret;
} else {
/* we do it the old way, with the gpio pin */
kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
/* small delay for the pulse */
udelay(10);
kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
}
return 0;
}
int fpga_reset(void)
{
if (!check_boco2()) {
/* we do not have BOCO2, this is not really used */
return 0;
}
printf("PCIe reset through GPIO7: ");
/* apply PCIe reset via GPIO */
kw_gpio_set_valid(KM_PEX_RST_GPIO_PIN, 1);
kw_gpio_direction_output(KM_PEX_RST_GPIO_PIN, 1);
kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 0);
udelay(1000*10);
kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 1);
printf(" done\n");
return 0;
}
