void dram_init_banksize(void)
{
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = kw_sdram_bar(i);
gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
kw_sdram_bs(i));
}
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
/*
* The KM_FLASH_GPIO_PIN switches between using a
* NAND or a SPI FLASH. Set this pin on start
* to NAND mode.
*/
kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
#if defined(CONFIG_SOFT_I2C)
/*
* Reinit the GPIO for I2C Bitbang driver so that the now
* available gpio framework is consistent. The calls to
* direction output in are not necessary, they are already done in
* board_early_init_f
*/
kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
#endif
#if defined(CONFIG_SYS_EEPROM_WREN)
kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
#endif
#if defined(CONFIG_KM_FPGA_CONFIG)
trigger_fpga_config();
#endif
return 0;
}
int board_init(void)
{
/* Boot parameters address */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
return 0;
}
int dram_init(void)
{
int i;
gd->ram_size = 0;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = kw_sdram_bar(i);
gd->bd->bi_dram[i].size = kw_sdram_bs(i);
/*
* It is assumed that all memory banks are consecutive
* and without gaps.
* If the gap is found, ram_size will be reported for
* consecutive memory only
*/
if (gd->bd->bi_dram[i].start != gd->ram_size)
break;
gd->ram_size += gd->bd->bi_dram[i].size;
}
for (; i < CONFIG_NR_DRAM_BANKS; i++) {
/* If above loop terminated prematurely, we need to set
* remaining banks' start address & size as 0. Otherwise other
* u-boot functions and Linux kernel gets wrong values which
* could result in crash */
gd->bd->bi_dram[i].start = 0;
gd->bd->bi_dram[i].size = 0;
}
return 0;
}
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
/* Fix this */
gd->ram_size = get_ram_size((volatile void *)kw_sdram_bar(0),
kw_sdram_bs(0));
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
set_led(LED_POWER_BLINKING);
return 0;
}
void kw_sdram_size_adjust(enum memory_bank bank)
{
u32 size;
/* probe currently equipped RAM size */
size = get_ram_size((void *)kw_sdram_bar(bank), kw_sdram_bs(bank));
/* adjust SDRAM window size accordingly */
kw_sdram_bs_set(bank, size);
}
int board_init(void)
{
/* Machine number */
gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2;
/* Boot parameters address */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
return 0;
}
int dram_init(void)
{
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = kw_sdram_bar(i);
gd->bd->bi_dram[i].size = kw_sdram_bs(i);
}
return 0;
}
int board_init(void)
{
/*
* arch number of board
*/
gd->bd->bi_arch_number = MACH_TYPE_RD88F6281;
/* adress of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
return 0;
}
int board_init(void)
{
/*
* arch number of board
*/
#if defined(CONFIG_BOARD_IS_OPENRD_BASE)
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
#endif
/* adress of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
return 0;
}
static void set_dram_access(struct kwgbe_registers *regs)
{
struct kwgbe_winparam win_param;
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
/* Set access parameters for DRAM bank i */
win_param.win = i; /* Use Ethernet window i */
/* Window target - DDR */
win_param.target = KWGBE_TARGET_DRAM;
/* Enable full access */
win_param.access_ctrl = EWIN_ACCESS_FULL;
win_param.high_addr = 0;
/* Get bank base */
win_param.base_addr = kw_sdram_bar(i);
win_param.size = kw_sdram_bs(i); /* Get bank size */
if (win_param.size == 0)
win_param.enable = 0;
else
win_param.enable = 1; /* Enable the access */
/* Enable DRAM bank */
switch (i) {
case 0:
win_param.attrib = EBAR_DRAM_CS0;
break;
case 1:
win_param.attrib = EBAR_DRAM_CS1;
break;
case 2:
win_param.attrib = EBAR_DRAM_CS2;
break;
case 3:
win_param.attrib = EBAR_DRAM_CS3;
break;
default:
/* invalide bank, disable access */
win_param.enable = 0;
win_param.attrib = 0;
break;
}
/* Set the access control for address window(EPAPR) RD/WR */
set_access_control(regs, &win_param);
}
}
int board_init(void)
{
u32 tmp;
kirkwood_mpp_conf(kwmpp_config);
/*
* The FLASH_GPIO_PIN switches between using a
* NAND or a SPI FLASH. Set this pin on start
* to NAND mode.
*/
tmp = readl(KW_GPIO0_BASE);
writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
tmp = readl(KW_GPIO0_BASE + 4);
writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
printf("KM: setting NAND mode\n");
/*
* arch number of board
*/
gd->bd->bi_arch_number = MACH_TYPE_SUEN3;
/* address of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
#if defined(CONFIG_SOFT_I2C)
/* init the GPIO for I2C Bitbang driver */
kw_gpio_set_valid(SUEN3_SDA_PIN, 1);
kw_gpio_set_valid(SUEN3_SCL_PIN, 1);
kw_gpio_direction_output(SUEN3_SDA_PIN, 0);
kw_gpio_direction_output(SUEN3_SCL_PIN, 0);
#endif
#if defined(CONFIG_SYS_EEPROM_WREN)
kw_gpio_set_valid(SUEN3_ENV_WP, 38);
kw_gpio_direction_output(SUEN3_ENV_WP, 1);
#endif
return 0;
}
/*
* USB 2.0 Bridge Address Decoding registers setup
*/
static void usb_brg_adrdec_setup(void)
{
int i;
u32 size, attrib;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
/* Enable DRAM bank */
switch (i) {
case 0:
attrib = KWCPU_ATTR_DRAM_CS0;
break;
case 1:
attrib = KWCPU_ATTR_DRAM_CS1;
break;
case 2:
attrib = KWCPU_ATTR_DRAM_CS2;
break;
case 3:
attrib = KWCPU_ATTR_DRAM_CS3;
break;
default:
/* invalide bank, disable access */
attrib = 0;
break;
}
size = kw_sdram_bs(i);
if ((size) && (attrib))
wrl(USB_WINDOW_CTRL(i),
KWCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
attrib, KWCPU_WIN_ENABLE));
else
wrl(USB_WINDOW_CTRL(i), KWCPU_WIN_DISABLE);
wrl(USB_WINDOW_BASE(i), kw_sdram_bar(i));
}
}
int board_init(void)
{
/*
* default gpio configuration
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
kw_config_gpio(OPENRD_OE_VAL_LOW,
OPENRD_OE_VAL_HIGH,
OPENRD_OE_LOW, OPENRD_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MPP3_NF_IO5,
MPP4_NF_IO6,
MPP5_NF_IO7,
MPP6_SYSRST_OUTn,
MPP7_GPO,
MPP8_TW_SDA,
MPP9_TW_SCK,
MPP10_UART0_TXD,
MPP11_UART0_RXD,
MPP12_SD_CLK,
MPP13_SD_CMD, /* Alt UART1_TXD */
MPP14_SD_D0, /* Alt UART1_RXD */
MPP15_SD_D1,
MPP16_SD_D2,
MPP17_SD_D3,
MPP18_NF_IO0,
MPP19_NF_IO1,
MPP20_GE1_0,
MPP21_GE1_1,
MPP22_GE1_2,
MPP23_GE1_3,
MPP24_GE1_4,
MPP25_GE1_5,
MPP26_GE1_6,
MPP27_GE1_7,
MPP28_GPIO,
MPP29_TSMP9,
MPP30_GE1_10,
MPP31_GE1_11,
MPP32_GE1_12,
MPP33_GE1_13,
MPP34_GPIO, /* UART1 / SD sel */
MPP35_TDM_CH0_TX_QL,
MPP36_TDM_SPI_CS1,
MPP37_TDM_CH2_TX_QL,
MPP38_TDM_CH2_RX_QL,
MPP39_AUDIO_I2SBCLK,
MPP40_AUDIO_I2SDO,
MPP41_AUDIO_I2SLRC,
MPP42_AUDIO_I2SMCLK,
MPP43_AUDIO_I2SDI,
MPP44_AUDIO_EXTCLK,
MPP45_TDM_PCLK,
MPP46_TDM_FS,
MPP47_TDM_DRX,
MPP48_TDM_DTX,
MPP49_TDM_CH0_RX_QL,
0
};
kirkwood_mpp_conf(kwmpp_config);
/*
* arch number of board
*/
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
/* adress of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
return 0;
}
int board_init(void)
{
/*
* default gpio configuration
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
kw_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW,
MV88F6281GTW_GE_OE_VAL_HIGH,
MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
u32 kwmpp_config[] = {
MPP0_SPI_SCn,
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
MPP3_SPI_MISO,
MPP4_GPIO,
MPP5_GPO,
MPP6_SYSRST_OUTn,
MPP7_SPI_SCn,
MPP8_TW_SDA,
MPP9_TW_SCK,
MPP10_UART0_TXD,
MPP11_UART0_RXD,
MPP12_GPO,
MPP13_GPIO,
MPP14_GPIO,
MPP15_GPIO,
MPP16_GPIO,
MPP17_GPIO,
MPP18_GPO,
MPP19_GPO,
MPP20_GPIO,
MPP21_GPIO,
MPP22_GPIO,
MPP23_GPIO,
MPP24_GPIO,
MPP25_GPIO,
MPP26_GPIO,
MPP27_GPIO,
MPP28_GPIO,
MPP29_GPIO,
MPP30_GPIO,
MPP31_GPIO,
MPP32_GPIO,
MPP33_GPIO,
MPP34_GPIO,
MPP35_GPIO,
MPP36_GPIO,
MPP37_GPIO,
MPP38_GPIO,
MPP39_GPIO,
MPP40_GPIO,
MPP41_GPIO,
MPP42_GPIO,
MPP43_GPIO,
MPP44_GPIO,
MPP45_GPIO,
MPP46_GPIO,
MPP47_GPIO,
MPP48_GPIO,
MPP49_GPIO,
0
};
kirkwood_mpp_conf(kwmpp_config);
/*
* arch number of board
*/
gd->bd->bi_arch_number = MACH_TYPE_MV88F6281GTW_GE;
/* adress of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
return 0;
}
int board_init(void)
{
/*
* default gpio configuration
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
kw_config_gpio(GURUPLUG_OE_VAL_LOW,
GURUPLUG_OE_VAL_HIGH,
GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MPP3_NF_IO5,
MPP4_NF_IO6,
MPP5_NF_IO7,
MPP6_SYSRST_OUTn,
MPP7_GPO, /* GPIO_RST */
MPP8_TW_SDA,
MPP9_TW_SCK,
MPP10_UART0_TXD,
MPP11_UART0_RXD,
MPP12_SD_CLK,
MPP13_SD_CMD,
MPP14_SD_D0,
MPP15_SD_D1,
MPP16_SD_D2,
MPP17_SD_D3,
MPP18_NF_IO0,
MPP19_NF_IO1,
MPP20_GE1_0,
MPP21_GE1_1,
MPP22_GE1_2,
MPP23_GE1_3,
MPP24_GE1_4,
MPP25_GE1_5,
MPP26_GE1_6,
MPP27_GE1_7,
MPP28_GE1_8,
MPP29_GE1_9,
MPP30_GE1_10,
MPP31_GE1_11,
MPP32_GE1_12,
MPP33_GE1_13,
MPP34_GE1_14,
MPP35_GE1_15,
MPP36_GPIO,
MPP37_GPIO,
MPP38_GPIO,
MPP39_GPIO,
MPP40_TDM_SPI_SCK,
MPP41_TDM_SPI_MISO,
MPP42_TDM_SPI_MOSI,
MPP43_GPIO,
MPP44_GPIO,
MPP45_GPIO,
MPP46_GPIO, /* M_RLED */
MPP47_GPIO, /* M_GLED */
MPP48_GPIO, /* B_RLED */
MPP49_GPIO, /* B_GLED */
0
};
kirkwood_mpp_conf(kwmpp_config);
/*
* arch number of board
*/
gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG;
/* adress of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
return 0;
}
