void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/* At this stage the main oscillator is supposed
* to be enabled PCK = MCK = MOSC
*/
/* Switch PCK/MCK on Main clock output */
pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK);
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS);
/* Initialize PLLA charge pump */
/* not needed for SAMA5D4 */
pmc_init_pll(0);
/* Switch MCK on PLLA output */
pmc_cfg_mck(BOARD_PRESCALER_PLLA);
/* Enable External Reset */
writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN,
AT91C_BASE_RSTC + RSTC_RMR);
#if defined(CONFIG_ENTER_NWD)
cpacr_init();
/* Program the DACR to allow client access to *all* domains */
dacr_swd_init();
#endif
#if defined(CONFIG_MATRIX)
/* Initialize the matrix */
matrix_init();
#endif
/* initialize the dbgu */
initialize_dbgu();
#if defined(CONFIG_MATRIX)
matrix_read_slave_security();
matrix_read_periperal_security();
#endif
/* Init timer */
timer_init();
#ifdef CONFIG_DDR2
/* Initialize MPDDR Controller */
ddramc_init();
#endif
/* Prepare L2 cache setup */
l2cache_prepare();
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/*
* while coming from the ROM code, we run on PLLA @ 396 MHz / 132 MHz
* so we need to slow down and configure MCKR accordingly.
* This is why we have a special flavor of the switching function.
*/
/* Switch PCK/MCK on Main Clock output */
pmc_cfg_mck_down(BOARD_PRESCALER_MAIN_CLOCK);
/* Configure PLLA */
pmc_cfg_plla(PLLA_SETTINGS);
/* Initialize PLLA charge pump */
/* No need: we keep what is set in ROM code */
//pmc_init_pll(0x3);
/* Switch MCK on PLLA output */
pmc_cfg_mck(BOARD_PRESCALER_PLLA);
/* Enable External Reset */
writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN,
AT91C_BASE_RSTC + RSTC_RMR);
#if defined(CONFIG_MATRIX)
/* Initialize the matrix */
matrix_init();
#endif
/* initialize the dbgu */
initialize_dbgu();
/* Init timer */
timer_init();
#if defined(CONFIG_DDR3)
/* Initialize MPDDR Controller */
ddramc_init();
#elif defined(CONFIG_LPDDR1)
lpddr1_init();
#elif defined(CONFIG_LPDDR2)
lpddr2_init();
#elif defined(CONFIG_LPDDR3)
lpddr3_init();
#endif
/* Prepare L2 cache setup */
l2cache_prepare();
at91_init_can_message_ram();
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/*
* while coming from the ROM code, we run on PLLA @ 396 MHz / 132 MHz
* so we need to slow down and configure MCKR accordingly.
* This is why we have a special flavor of the switching function.
*/
/* Switch PCK/MCK clock source to the main clock */
pmc_cfg_mck_down(BOARD_PRESCALER_MAIN_CLOCK);
/* Configure PLLA */
pmc_cfg_plla(PLLA_SETTINGS);
/* Switch MCK clock source to PLLA */
pmc_cfg_mck(BOARD_PRESCALER_PLLA);
/* Enable external reset */
writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN,
AT91C_BASE_RSTC + RSTC_RMR);
#if defined(CONFIG_MATRIX)
/* Initialize the matrix */
matrix_init();
#endif
/* initialize the dbgu */
initialize_dbgu();
/* Init timer */
timer_init();
#if defined(CONFIG_DDR3)
/* Initialize MPDDR Controller */
ddramc_init();
#endif
/* Prepare L2 cache setup */
l2cache_prepare();
}