void mainboard_smi_sleep(uint8_t slp_typ)
{
/* Disable USB charging if required */
switch (slp_typ) {
case 3:
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s3u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
if (smm_get_gnvs()->s3u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
#endif
/* Enable wake pin in GPE block. */
enable_gpe(WAKE_GPIO_EN);
break;
case 5:
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s5u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
if (smm_get_gnvs()->s5u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
#endif
break;
}
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
while (google_chromeec_get_event() != 0)
;
if (smm_get_gnvs()->bdid == BOARD_DVT) {
/* Set LPC lines to low power in S3/S5. */
if ((slp_typ == SLEEP_STATE_S3) || (slp_typ == SLEEP_STATE_S5))
lpc_set_low_power();
}
#endif
}
void mainboard_smi_sleep(uint8_t slp_typ)
{
void *addr;
uint32_t mask;
/* Disable USB charging if required */
switch (slp_typ) {
case 3:
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s3u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
if (smm_get_gnvs()->s3u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
#endif
/* Enable wake pin in GPE block. */
enable_gpe(WAKE_GPIO_EN);
break;
case 5:
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s5u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
if (smm_get_gnvs()->s5u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
#endif
/* Disabling wake from SUS_GPIO1 (TOUCH INT) and
* SUS_GPIO7 (TRACKPAD INT) in North bank as they are not
* valid S5 wake sources
*/
addr = (void *)(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPNORTH +
GPIO_WAKE_MASK_REG0);
mask = ~(GPIO_SUS1_WAKE_MASK | GPIO_SUS7_WAKE_MASK);
write32(addr, read32(addr) & mask);
break;
}
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
while (google_chromeec_get_event() != 0)
;
if (smm_get_gnvs()->bdid == BOARD_PRE_EVT) {
/* Set LPC lines to low power in S3/S5. */
if ((slp_typ == SLEEP_STATE_S3) || (slp_typ == SLEEP_STATE_S5))
lpc_set_low_power();
}
#endif
}
