static void lpddr2_init(void)
{
struct ddramc_register ddramc_reg;
unsigned int reg;
lpddr2_reg_config(&ddramc_reg);
pmc_enable_periph_clock(AT91C_ID_MPDDRC);
pmc_enable_system_clock(AT91C_PMC_DDR);
/*
* Initialize the special register for the SAMA5D3X_CMP.
* MPDDRC DLL Slave Offset Register: DDR2 configuration
*/
reg = AT91C_MPDDRC_S0OFF(0x04)
| AT91C_MPDDRC_S1OFF(0x03)
| AT91C_MPDDRC_S2OFF(0x04)
| AT91C_MPDDRC_S3OFF(0x04);
writel(reg, (AT91C_BASE_MPDDRC + MPDDRC_DLL_SOR));
/*
* MPDDRC DLL Master Offset Register
* write master + clk90 offset
*/
reg = AT91C_MPDDRC_MOFF(7)
| AT91C_MPDDRC_CLK90OFF(0x1F)
| AT91C_MPDDRC_SELOFF_ENABLED | AT91C_MPDDRC_KEY;
writel(reg, (AT91C_BASE_MPDDRC + MPDDRC_DLL_MOR));
/*
* MPDDRC I/O Calibration Register
* DDR2 RZQ = 50 Ohm
* TZQIO = 4
*/
reg = readl(AT91C_BASE_MPDDRC + MPDDRC_IO_CALIBR);
reg &= ~AT91C_MPDDRC_RDIV;
reg &= ~AT91C_MPDDRC_TZQIO;
reg |= AT91C_MPDDRC_RDIV_DDR2_RZQ_50;
reg |= AT91C_MPDDRC_TZQIO_3;
writel(reg, (AT91C_BASE_MPDDRC + MPDDRC_IO_CALIBR));
lpddr2_sdram_initialize(AT91C_BASE_MPDDRC,
AT91C_BASE_DDRCS, &ddramc_reg);
}
static void lpddr2_init(void)
{
struct ddramc_register ddramc_reg;
unsigned int reg;
pmc_enable_periph_clock(AT91C_ID_MPDDRC);
pmc_enable_system_clock(AT91C_PMC_DDR);
reg = readl(AT91C_BASE_MPDDRC + MPDDRC_IO_CALIBR);
reg &= ~AT91C_MPDDRC_RDIV;
reg &= ~AT91C_MPDDRC_TZQIO;
reg |= AT91C_MPDDRC_RDIV_LPDDR2_RZQ_48;
reg |= AT91C_MPDDRC_TZQIO_(100);
writel(reg, (AT91C_BASE_MPDDRC + MPDDRC_IO_CALIBR));
writel(AT91C_MPDDRC_RD_DATA_PATH_THREE_CYCLES,
AT91C_BASE_MPDDRC + MPDDRC_RD_DATA_PATH);
lpddr2_reg_config(&ddramc_reg);
lpddr2_sdram_initialize(AT91C_BASE_MPDDRC,
AT91C_BASE_DDRCS, &ddramc_reg);
}
