int board_init(void)
{
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_SFFSDR;
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
davinci_errata_workarounds();
/* Power on required peripherals */
lpsc_on(DAVINCI_LPSC_GPIO);
#if !defined(CONFIG_SYS_USE_DSPLINK)
/* Powerup the DSP */
dsp_on();
#endif /* CONFIG_SYS_USE_DSPLINK */
davinci_enable_uart0();
davinci_enable_emac();
davinci_enable_i2c();
lpsc_on(DAVINCI_LPSC_TIMER1);
timer_init();
return(0);
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
/* Configure AEMIF pins (although this should be configured at boot time
* with pull-up/pull-down resistors) */
REG(PINMUX0) = 0x00000c1f;
davinci_errata_workarounds();
/* Power on required peripherals */
lpsc_on(DAVINCI_LPSC_GPIO);
#if !defined(CONFIG_SYS_USE_DSPLINK)
/* Powerup the DSP */
dsp_on();
#endif /* CONFIG_SYS_USE_DSPLINK */
davinci_enable_uart0();
davinci_enable_emac();
davinci_enable_i2c();
lpsc_on(DAVINCI_LPSC_TIMER1);
timer_init();
return(0);
}
int dm365_ddr_setup(void)
{
lpsc_on(DAVINCI_LPSC_DDR_EMIF);
clrbits_le32(&dv_sys_module_regs->vtpiocr,
VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN);
/* Set bit CLRZ (bit 13) */
setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);
/* Check VTP READY Status */
while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY))
;
/* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);
/* Set bit LOCK(bit7) */
setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);
/*
* Powerdown VTP as it is locked (bit 6)
* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
*/
setbits_le32(&dv_sys_module_regs->vtpiocr,
VPTIO_IOPWRDN | VPTIO_PWRDN);
/* Wait for calibration to complete */
dm365_waitloop(150);
/* Set the DDR2 to synreset, then enable it again */
lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
lpsc_on(DAVINCI_LPSC_DDR_EMIF);
writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
/* Program SDRAM Bank Config Register */
writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK),
&dv_ddr2_regs_ctrl->sdbcr);
writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK),
&dv_ddr2_regs_ctrl->sdbcr);
/* Program SDRAM Timing Control Register1 */
writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
/* Program SDRAM Timing Control Register2 */
writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
/* Program SDRAM Refresh Control Register */
writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);
lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
lpsc_on(DAVINCI_LPSC_DDR_EMIF);
return 0;
}
void davinci_enable_emac(void)
{
lpsc_on(DAVINCI_LPSC_EMAC);
lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
lpsc_on(DAVINCI_LPSC_MDIO);
/* Enable GIO3.3V cells used for EMAC */
REG(VDD3P3V_PWDN) = 0;
/* Enable EMAC. */
REG(PINMUX0) |= PINMUX0_EMACEN;
}
int usb_cpu_init(void)
{
/* enable psc for usb2.0 */
lpsc_on(DAVINCI_LPSC_USB20);
/* enable psc for usb1.0 */
lpsc_on(DAVINCI_LPSC_USB11);
/* start the on-chip usb phy and its pll */
if (usb_phy_on())
return 0;
return 1;
}
void davinci_enable_i2c(void)
{
lpsc_on(DAVINCI_LPSC_I2C);
/* Enable I2C pin Mux */
REG(PINMUX1) |= PINMUX1_I2C;
}
/*
* This function performs DA8xx platform specific initialization for usb0.
*/
int musb_platform_init(void)
{
u32 revision;
/* enable psc for usb2.0 */
lpsc_on(33);
/* enable usb vbus */
enable_vbus();
/* reset the controller */
writel(0x1, &da8xx_usb_regs->control);
udelay(5000);
/* start the on-chip usb phy and its pll */
if (phy_on() == 0)
return -1;
/* Returns zero if e.g. not clocked */
revision = readl(&da8xx_usb_regs->revision);
if (revision == 0)
return -1;
/* Disable all interrupts */
writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK |
DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_set);
return 0;
}
void davinci_enable_i2c(void)
{
lpsc_on(DAVINCI_LPSC_I2C);
/* Enable I2C pin Mux */
REG(PINMUX3) |= (1 << 20) | (1 << 19);
}
void davinci_enable_uart0(void)
{
lpsc_on(DAVINCI_LPSC_UART0);
/* Bringup UART0 out of reset */
REG(UART0_PWREMU_MGMT) = 0x00006001;
}
void davinci_enable_uart0(void)
{
lpsc_on(DAVINCI_LPSC_UART0);
/* Bringup UART0 out of reset */
REG(UART0_PWREMU_MGMT) = 0x00006001;
/* Enable UART0 MUX lines */
REG(PINMUX1) |= PINMUX1_UART0;
}
/* read board revision from GPIO7[8..14] */
u32 get_board_rev(void)
{
lpsc_on(DAVINCI_LPSC_GPIO);
if (davinci_configure_pin_mux(hwversion_pins,
ARRAY_SIZE(hwversion_pins)) != 0)
return 0xffffffff;
return (davinci_gpio_bank67->in_data & CALIMAIN_HWVERSION_MASK)
>> CALIMAIN_HWVERSION_SHIFT;
}
/*
* Enable PSC for various peripherals.
*/
int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
const int n_items)
{
int i;
for (i = 0; i < n_items; i++)
lpsc_on(item[i].lpsc_no);
return 0;
}
int board_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM355_EVM;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
/* We expect the UBL to have handled "lowlevel init", which
* involves setting up at least:
* - clocks
* + PLL1 (for ARM and peripherals) and PLL2 (for DDR)
* + clock divisors for those PLLs
* + LPSC_DDR module enabled
* + LPSC_TIMER0 module (still) enabled
* - EMIF
* + DDR init and timings
* + AEMIF timings (for NAND and DM9000)
* - pinmux
*
* Some of that is repeated here, mostly as a precaution.
*/
/* AEMIF: Some "address" lines are available as GPIOs. A3..A13
* could be too if we used A12 as a GPIO during NAND chipselect
* (and Linux did too), letting us control the LED on A7/GPIO61.
*/
REG(PINMUX2) = 0x0c08;
/* UART0 may still be in SyncReset if we didn't boot from UART */
davinci_enable_uart0();
/* EDMA may be in SyncReset too; turn it on, Linux won't (yet) */
lpsc_on(DAVINCI_LPSC_TPCC);
lpsc_on(DAVINCI_LPSC_TPTC0);
lpsc_on(DAVINCI_LPSC_TPTC1);
return 0;
}
int board_init(void)
{
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
/* Workaround for TMS320DM6446 errata 1.3.22 */
REG(PSC_SILVER_BULLET) = 0;
/* Power on required peripherals */
lpsc_on(DAVINCI_LPSC_EMAC);
lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
lpsc_on(DAVINCI_LPSC_MDIO);
lpsc_on(DAVINCI_LPSC_I2C);
lpsc_on(DAVINCI_LPSC_UART0);
lpsc_on(DAVINCI_LPSC_TIMER1);
lpsc_on(DAVINCI_LPSC_GPIO);
/* Powerup the DSP */
dsp_on();
/* Bringup UART0 out of reset */
REG(UART0_PWREMU_MGMT) = 0x0000e003;
/* Enable GIO3.3V cells used for EMAC */
REG(VDD3P3V_PWDN) = 0;
/* Enable UART0 MUX lines */
REG(PINMUX1) |= 1;
/* Enable EMAC and AEMIF pins */
REG(PINMUX0) = 0x80000c1f;
/* Enable I2C pin Mux */
REG(PINMUX1) |= (1 << 7);
/* Set the Bus Priority Register to appropriate value */
REG(VBPR) = 0x20;
timer_init();
return(0);
}
int board_init(void)
{
unsigned int temp;
int j;
#ifndef CONFIG_USE_IRQ
/*
* Mask all IRQs by clearing the global enable and setting
* the enable clear for all the 90 interrupts.
*/
writel(0, &davinci_aintc_regs->ger);
writel(0, &davinci_aintc_regs->hier);
writel(0xffffffff, &davinci_aintc_regs->ecr1);
writel(0xffffffff, &davinci_aintc_regs->ecr2);
writel(0xffffffff, &davinci_aintc_regs->ecr3);
#endif
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
/*
* Power on required peripherals
* ARM does not have access by default to PSC0 and PSC1
* assuming here that the DSP bootloader has set the IOPU
* such that PSC access is available to ARM
*/
lpsc_on(DAVINCI_LPSC_AEMIF); /* NAND, NOR */
lpsc_on(DAVINCI_LPSC_SPI1); /* Serial Flash */
lpsc_on(DAVINCI_LPSC_EMAC); /* image download */
lpsc_on(DAVINCI_LPSC_UART2); /* console */
lpsc_on(DAVINCI_LPSC_GPIO);
#ifdef CONFIG_DAVINCI_MMC
lpsc_on(DAVINCI_LPSC_MMC_SD);
#endif
/* setup the SUSPSRC for ARM to control emulation suspend */
writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
DAVINCI_SYSCFG_SUSPSRC_UART2),
&davinci_syscfg_regs->suspsrc);
#ifdef CONFIG_SPI_FLASH
if (davinci_configure_pin_mux(spi1_pins, ARRAY_SIZE(spi1_pins)) != 0)
return 1;
#endif
#ifdef CONFIG_DAVINCI_MMC
if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0)
return 1;
/* Set the GPIO direction as output */
temp = REG(GPIO_BANK0_REG_DIR_ADDR);
temp &= ~(0x01 << 11);
REG(GPIO_BANK0_REG_DIR_ADDR) = temp;
/* Set the output as high */
temp = REG(GPIO_BANK0_REG_SET_ADDR);
temp |= (0x01 << 11);
REG(GPIO_BANK0_REG_SET_ADDR) = temp;
#endif
if (davinci_configure_pin_mux(uart_pins, ARRAY_SIZE(uart_pins)) != 0)
return 1;
if (davinci_configure_pin_mux(i2c_pins, ARRAY_SIZE(i2c_pins)) != 0)
return 1;
#ifdef CONFIG_DRIVER_TI_EMAC
if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
return 1;
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
REG(CFGCHIP3) |= (1 << 8);
#else
/* set cfgchip3 to selct MII */
REG(CFGCHIP3) &= ~(1 << 8);
#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
#endif /* CONFIG_DRIVER_TI_EMAC */
#ifdef CONFIG_USE_NAND
if (davinci_configure_pin_mux(aemif_pins, ARRAY_SIZE(aemif_pins)) != 0)
return 1;
#elif defined(CONFIG_SYS_USE_NOR)
if (davinci_configure_pin_mux(nor_pins, ARRAY_SIZE(nor_pins)) != 0)
return 1;
/* Set the GPIO direction as output */
temp = REG(GPIO_BANK0_REG_DIR_ADDR);
temp &= ~(0x01 << 11);
REG(GPIO_BANK0_REG_DIR_ADDR) = temp;
/* Set the output as low */
temp = REG(GPIO_BANK0_REG_SET_ADDR);
temp |= (0x01 << 11);
REG(GPIO_BANK0_REG_CLR_ADDR) = temp;
#endif
/*
* If we boot over UART, Terminal doesn't display characters
* Reset the values set by Boot ROM
*/
for(j=0;j<15;){
REG(DAVINCI_UART2_BASE + (j*4)) = 0;
j=j+1;
}
/* enable the console UART */
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
&davinci_uart2_ctrl_regs->pwremu_mgmt);
if (davinci_configure_pin_mux(button_pins, ARRAY_SIZE(button_pins)) != 0)
return 1;
return(0);
}
int board_init(void)
{
#ifndef CONFIG_USE_IRQ
/*
* Mask all IRQs by clearing the global enable and setting
* the enable clear for all the 90 interrupts.
*/
writel(0, &davinci_aintc_regs->ger);
writel(0, &davinci_aintc_regs->hier);
writel(0xffffffff, &davinci_aintc_regs->ecr1);
writel(0xffffffff, &davinci_aintc_regs->ecr2);
writel(0xffffffff, &davinci_aintc_regs->ecr3);
#endif
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM;
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
/*
* Power on required peripherals
* ARM does not have access by default to PSC0 and PSC1
* assuming here that the DSP bootloader has set the IOPU
* such that PSC access is available to ARM
*/
lpsc_on(DAVINCI_LPSC_AEMIF); /* NAND, NOR */
lpsc_on(DAVINCI_LPSC_SPI0); /* Serial Flash */
lpsc_on(DAVINCI_LPSC_EMAC); /* image download */
lpsc_on(DAVINCI_LPSC_UART2); /* console */
lpsc_on(DAVINCI_LPSC_GPIO);
/* setup the SUSPSRC for ARM to control emulation suspend */
writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
DAVINCI_SYSCFG_SUSPSRC_UART2),
&davinci_syscfg_regs->suspsrc);
#ifdef CONFIG_SPI_FLASH
if (davinci_configure_pin_mux(spi0_pins, ARRAY_SIZE(spi0_pins)) != 0)
return 1;
#endif
if (davinci_configure_pin_mux(uart_pins, ARRAY_SIZE(uart_pins)) != 0)
return 1;
if (davinci_configure_pin_mux(i2c_pins, ARRAY_SIZE(i2c_pins)) != 0)
return 1;
if (davinci_configure_pin_mux(usb_pins, ARRAY_SIZE(usb_pins)) != 0)
return 1;
/* enable the console UART */
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
&davinci_uart2_ctrl_regs->pwremu_mgmt);
return(0);
}
int board_init(void)
{
#ifndef CONFIG_USE_IRQ
/*
* Mask all IRQs by clearing the global enable and setting
* the enable clear for all the 90 interrupts.
*/
writel(0, &davinci_aintc_regs->ger);
writel(0, &davinci_aintc_regs->hier);
writel(0xffffffff, &davinci_aintc_regs->ecr1);
writel(0xffffffff, &davinci_aintc_regs->ecr2);
writel(0xffffffff, &davinci_aintc_regs->ecr3);
#endif
#ifdef CONFIG_NAND_DAVINCI
/* EMIFA 100MHz clock select */
writel(readl(&davinci_syscfg_regs->cfgchip3) & ~2,
&davinci_syscfg_regs->cfgchip3);
/* NAND CS setup */
writel((DAVINCI_ABCR_WSETUP(0) |
DAVINCI_ABCR_WSTROBE(2) |
DAVINCI_ABCR_WHOLD(0) |
DAVINCI_ABCR_RSETUP(0) |
DAVINCI_ABCR_RSTROBE(2) |
DAVINCI_ABCR_RHOLD(0) |
DAVINCI_ABCR_TA(2) |
DAVINCI_ABCR_ASIZE_8BIT),
&davinci_emif_regs->AB2CR);
#endif
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM;
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
/*
* Power on required peripherals
* ARM does not have access by default to PSC0 and PSC1
* assuming here that the DSP bootloader has set the IOPU
* such that PSC access is available to ARM
*/
lpsc_on(DAVINCI_LPSC_AEMIF); /* NAND, NOR */
lpsc_on(DAVINCI_LPSC_SPI0); /* Serial Flash */
lpsc_on(DAVINCI_LPSC_EMAC); /* image download */
lpsc_on(DAVINCI_LPSC_UART2); /* console */
lpsc_on(DAVINCI_LPSC_GPIO);
/* setup the SUSPSRC for ARM to control emulation suspend */
writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
DAVINCI_SYSCFG_SUSPSRC_UART2),
&davinci_syscfg_regs->suspsrc);
/* configure pinmux settings */
if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
return 1;
/* enable the console UART */
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
&davinci_uart2_ctrl_regs->pwremu_mgmt);
return(0);
}
void davinci_enable_i2c(void)
{
lpsc_on(DAVINCI_LPSC_I2C);
}
void davinci_enable_uart0(void)
{
lpsc_on(DAVINCI_LPSC_UART0);
}
void davinci_enable_emac(void)
{
lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
}
