/* Cascaded interrupts from IM0 */
void danube_hw0_irqdispatch(struct pt_regs *regs)
{
u32 irq;
#ifdef IVEC_BUG_FIX
irq = (*DANUBE_ICU_IM0_IOSR);
/* if int_status == 0, then the interrupt has already been cleared */
if (irq == 0) {
return;
}
irq = ls1bit32(irq);
#else
irq = (*DANUBE_ICU_IM_VEC) & DANUBE_ICU_IM0_VEC_MASK;
if (irq ==0) return;
irq--;
#endif /*IVEC_BUG_FIX*/
//prochao+, 10/17/2006, for supporting the WiFi on the CPU1 core with another interrupt number
#ifdef CONFIG_DANUBE_CORE1
if (irq == INT_NUM_IM0_IRL26){ //on CPU1
#else
if (irq == INT_NUM_IM0_IRL22){ //on CPU0
#endif
/*clear EBU interrupt */
*(DANUBE_EBU_PCC_ISTAT) |= 0x10;
}
DANUBE_INT_DMSG("danube_hw0_irqdispatch: irq=%d\n", irq);
do_IRQ((int)irq, regs);
return;
}
/* Cascaded interrupts from IM1 */
void danube_hw1_irqdispatch(struct pt_regs *regs)
{
u32 irq;
#ifdef IVEC_BUG_FIX
irq = (*DANUBE_ICU_IM1_IOSR);
/* if int_status == 0, then the interrupt has already been cleared */
if (irq == 0) {
return;
}
irq = ls1bit32(irq)+32;
#else
irq = ((*DANUBE_ICU_IM_VEC) & DANUBE_ICU_IM4_VEC_MASK) >>6;
if (irq ==0) return;
irq+=31;
#endif /*IVEC_BUG_FIX*/
DANUBE_INT_DMSG("danube_hw1_irqdispatch: irq=%d\n", irq);
do_IRQ((int)irq, regs);
return;
}
void atlas_hw0_irqdispatch(struct pt_regs *regs)
{
struct irqaction *action;
unsigned long int_status;
int irq, cpu = smp_processor_id();
int_status = atlas_hw0_icregs->intstatus;
/* if int_status == 0, then the interrupt has already been cleared */
if (int_status == 0)
return;
irq = ls1bit32(int_status);
action = irq_desc[irq].action;
DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq);
/* if action == NULL, then we don't have a handler for the irq */
if ( action == NULL ) {
printk("No handler for hw0 irq: %i\n", irq);
spurious_count++;
return;
}
irq_enter(cpu, irq);
kstat.irqs[0][irq]++;
action->handler(irq, action->dev_id, regs);
irq_exit(cpu, irq);
return;
}
static void ralink_hw0_irqdispatch(int prio)
{
unsigned long int_status;
int irq;
if (prio)
int_status = *(volatile u32 *)(RALINK_IRQ1STAT);
else
int_status = *(volatile u32 *)(RALINK_IRQ0STAT);
if (int_status == 0)
return;
irq = ls1bit32(int_status);
/*
* Remapped IRQ 0..5 to 32..37:
* bit[5] UART: UARTF Interrupt Status after mask
* bit[4] PCM: PCM interrupt status after mask
* bit[3] ILL_ACC: Illegal access interrupt status after mask
* bit[2] WDTIMER: Timer 1 (Watchdog) timer interrupt status after mask
* bit[1] TIMER0: Timer 0 (DFS) interrupt status after mask
* bit[0] SYSCTL: System control interrupt status after mask
*/
if (irq < 6)
irq += 32;
do_IRQ(irq);
}
/*
* Interrupt handler for interrupts coming from the Marvell chip.
* It could be built in ethernet ports etc...
*/
void ll_mv64340_irq(struct pt_regs *regs)
{
unsigned int irq_src_low, irq_src_high;
unsigned int irq_mask_low, irq_mask_high;
/* read the interrupt status registers */
irq_mask_low = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW);
irq_mask_high = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH);
irq_src_low = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_LOW);
irq_src_high = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_HIGH);
/* mask for just the interrupts we want */
irq_src_low &= irq_mask_low;
irq_src_high &= irq_mask_high;
if (irq_src_low)
do_IRQ(ls1bit32(irq_src_low) + irq_base, regs);
else
do_IRQ(ls1bit32(irq_src_high) + irq_base + 32, regs);
}
void lasat_hw0_irqdispatch(struct pt_regs *regs)
{
unsigned long int_status;
int irq;
int_status = get_int_status();
/* if int_status == 0, then the interrupt has already been cleared */
if (int_status) {
irq = ls1bit32(int_status);
do_IRQ(irq, regs);
}
}
static inline void atlas_hw0_irqdispatch(struct pt_regs *regs)
{
unsigned long int_status;
int irq;
int_status = atlas_hw0_icregs->intstatus;
/* if int_status == 0, then the interrupt has already been cleared */
if (unlikely(int_status == 0))
return;
irq = ATLAS_INT_BASE + ls1bit32(int_status);
DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq);
do_IRQ(irq, regs);
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned long int_status;
unsigned int cause = read_c0_cause();
int irq;
if (cause & CAUSEF_IP7) { /* R4000 count / compare IRQ */
ll_timer_interrupt(7);
return;
}
int_status = get_int_status();
/* if int_status == 0, then the interrupt has already been cleared */
if (int_status) {
irq = ls1bit32(int_status);
do_IRQ(irq);
}
}
/* Cascaded interrupts from IM4 */
void danube_hw4_irqdispatch(struct pt_regs *regs)
{
u32 irq;
#ifdef IVEC_BUG_FIX
irq = (*DANUBE_ICU_IM4_IOSR);
/* if int_status == 0, then the interrupt has already been cleared */
if (irq == 0) {
return;
}
irq = ls1bit32(irq)+128;
#else
irq = ((*DANUBE_ICU_IM_VEC) & DANUBE_ICU_IM4_VEC_MASK) >>24;
if (irq ==0) return;
irq+=127;
#endif /*IVEC_BUG_FIX*/
DANUBE_INT_DMSG("danube_hw4_irqdispatch: irq=%d\n", irq);
do_IRQ((int)irq, regs);
return;
}
void surfboard_hw0_irqdispatch(void)
{
struct irqaction *action;
unsigned long int_status;
int irq;
int_status = surfboard_hw0_icregs->irq0Status;
/* if int_status == 0, then the interrupt has already been cleared */
if (int_status == 0)
return;
irq = ls1bit32(int_status);
// printk("-------------------------\n");
// printk("irqdispatch receive IRQ%d\n",irq);
// printk("-------------------------\n");
/*
* RT2880:
* bit[3] PIO Programmable IO Interrupt Status after Mask
* bit[2] UART Interrupt Status after Mask
* bit[1] WDTIMER Timer 1 Interrupt Status after Mask
* bit[0] TIMER0 Timer 0 Interrupt Status after Mask
*
* RT2883/RT3052:
* bit[17] Ethernet switch interrupt status after mask
* bit[6] PIO Programmable IO Interrupt Status after Mask
* bit[5] UART Interrupt Status after Mask
* bit[2] WDTIMER Timer 1 Interrupt Status after Mask
* bit[1] TIMER0 Timer 0 Interrupt Status after Mask
*/
#ifdef CONFIG_RALINK_TIMER_DFS
#if defined (CONFIG_RALINK_RT2880_SHUTTLE) || \
defined (CONFIG_RALINK_RT2880_MP)
if (irq == 0) {
#else
if (irq == 1) {
#endif
irq = SURFBOARDINT_TIMER0;
}
#endif
#if defined (CONFIG_RALINK_RT2880_SHUTTLE) || \
defined (CONFIG_RALINK_RT2880_MP)
if (irq == 3) {
#ifdef CONFIG_RALINK_GPIO
/* cause gpio registered irq 7 (see rt2880gpio_init_irq()) */
irq = SURFBOARDINT_GPIO;
printk("surfboard_hw0_irqdispatch(): INT #7...\n");
#else
printk("surfboard_hw0_irqdispatch(): External INT #3... surfboard discard!\n");
#endif
}
#else
/* ILL_ACC */
if (irq == 3) {
irq = SURFBOARDINT_ILL_ACC;
}
#endif
#if defined (CONFIG_RALINK_PCM) || defined (CONFIG_RALINK_PCM_MODULE)
/* PCM */
if (irq == 4) {
irq = SURFBOARDINT_PCM;
}
#endif
/* UARTF */
if (irq == 5) {
irq = SURFBOARDINT_UART;
}
action = irq_desc[irq].action;
do_IRQ(irq);
return;
}
static void enable_rt2880_cp_int(unsigned int IP_X)
{
unsigned long int_status;
int_status = read_32bit_cp0_register(CP0_STATUS);
int_status = int_status | IP_X ;
write_32bit_cp0_register(CP0_STATUS, int_status);
}
void surfboard_hw0_irqdispatch(void)
{
unsigned long int_status;
int irq;
int_status = *(volatile u32 *)(RALINK_IRQ0STAT);
/* if int_status == 0, then the interrupt has already been cleared */
if (unlikely(int_status == 0))
return;
irq = ls1bit32(int_status);
// printk("-------------------------\n");
// printk("irqdispatch receive IRQ%d\n",irq);
// printk("-------------------------\n");
/*
* RT2880:
* bit[3] PIO Programmable IO Interrupt Status after Mask
* bit[2] UART Interrupt Status after Mask
* bit[1] WDTIMER Timer 1 Interrupt Status after Mask
* bit[0] TIMER0 Timer 0 Interrupt Status after Mask
*
* RT2883/RT3052:
* bit[17] Ethernet switch interrupt status after mask
* bit[6] PIO Programmable IO Interrupt Status after Mask
* bit[5] UART Interrupt Status after Mask
* bit[2] WDTIMER Timer 1 Interrupt Status after Mask
* bit[1] TIMER0 Timer 0 Interrupt Status after Mask
*/
#if defined (CONFIG_RALINK_TIMER_DFS) || defined (CONFIG_RALINK_TIMER_DFS_MODULE)
#if defined (CONFIG_RALINK_RT2880_SHUTTLE) || \
defined (CONFIG_RALINK_RT2880_MP)
if (irq == 0) {
irq = SURFBOARDINT_TIMER0;
}
#else
if (irq == 1) {
irq = SURFBOARDINT_TIMER0;
}else if (irq == 2) {
irq = SURFBOARDINT_WDG;
}
#endif
#endif
#if defined (CONFIG_RALINK_RT2880_SHUTTLE) || \
defined (CONFIG_RALINK_RT2880_MP)
if (irq == 3) {
#ifdef CONFIG_RALINK_GPIO
/* cause gpio registered irq 7 (see rt2880gpio_init_irq()) */
irq = SURFBOARDINT_GPIO;
printk("surfboard_hw0_irqdispatch(): INT #7...\n");
#else
printk("surfboard_hw0_irqdispatch(): External INT #3... surfboard discard!\n");
#endif
}
#else
/* ILL_ACC */
if (irq == 3) {
irq = SURFBOARDINT_ILL_ACC;
}
#endif
#if defined (CONFIG_RALINK_PCM) || defined (CONFIG_RALINK_PCM_MODULE)
/* PCM */
if (irq == 4) {
irq = SURFBOARDINT_PCM;
}
#endif
/* UARTF */
if (irq == 5) {
irq = SURFBOARDINT_UART;
}
do_IRQ(irq);
return;
}
