/******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this is only intializes the MMU ******************************************************************************/ void tsp_plat_arch_setup(void) { ls_setup_page_tables(BL32_BASE, (BL32_END - BL32_BASE), BL_CODE_BASE, BL_CODE_END, BL_RO_DATA_BASE, BL_RO_DATA_END #if USE_COHERENT_MEM , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END #endif ); enable_mmu_el1(0); }
/******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this is only initializes the mmu in a quick and dirty way. ******************************************************************************/ void ls_bl2_plat_arch_setup(void) { ls_setup_page_tables(bl2_tzram_layout.total_base, bl2_tzram_layout.total_size, BL_CODE_BASE, BL_CODE_END, BL_RO_DATA_BASE, BL_RO_DATA_END #if USE_COHERENT_MEM , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END #endif ); #ifdef AARCH32 enable_mmu_svc_mon(0); #else enable_mmu_el1(0); #endif }