static int ltq_stp_hw_init(void) { /* the 3 pins used to control the external stp */ ltq_gpio_request(4, 1, 0, 1, "stp-st"); ltq_gpio_request(5, 1, 0, 1, "stp-d"); ltq_gpio_request(6, 1, 0, 1, "stp-sh"); /* sane defaults */ ltq_stp_w32(0, LTQ_STP_AR); ltq_stp_w32(0, LTQ_STP_CPU0); ltq_stp_w32(0, LTQ_STP_CPU1); ltq_stp_w32(LTQ_STP_CON_SWU, LTQ_STP_CON0); ltq_stp_w32(0, LTQ_STP_CON1); /* rising or falling edge */ ltq_stp_w32_mask(LTQ_STP_EDGE_MASK, LTQ_STP_FALLING, LTQ_STP_CON0); /* per default stp 15-0 are set */ ltq_stp_w32_mask(0, LTQ_STP_GROUP0, LTQ_STP_CON1); /* stp are update periodically by the FPI bus */ ltq_stp_w32_mask(LTQ_STP_UPD_MASK, LTQ_STP_UPD_FPI, LTQ_STP_CON1); /* set stp update speed */ ltq_stp_w32_mask(LTQ_STP_SPEED_MASK, LTQ_STP_8HZ, LTQ_STP_CON1); /* tell the hardware that pin (led) 0 and 1 are controlled * by the dsl arc */ ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0); ltq_pmu_enable(PMU_LED); return 0; }
int __init ltq_dma_init(void) { int i; /* insert and request the memory region */ if (insert_resource(&iomem_resource, <q_dma_resource) < 0) panic("Failed to insert dma memory\n"); if (request_mem_region(ltq_dma_resource.start, resource_size(<q_dma_resource), "dma") < 0) panic("Failed to request dma memory\n"); /* remap dma register range */ ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start, resource_size(<q_dma_resource)); if (!ltq_dma_membase) panic("Failed to remap dma memory\n"); /* power up and reset the dma engine */ ltq_pmu_enable(PMU_DMA); ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL); /* disable all interrupts */ ltq_dma_w32(0, LTQ_DMA_IRNEN); /* reset/configure each channel */ for (i = 0; i < DMA_MAX_CHANNEL; i++) { ltq_dma_w32(i, LTQ_DMA_CS); ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL); ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL); ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); } return 0; }
int ltq_dma_init(void) { int i; /* remap dma register range */ ltq_dma_membase = ltq_remap_resource(<q_dma_resource); if (!ltq_dma_membase) panic("Failed to remap dma memory\n"); /* power up and reset the dma engine */ ltq_pmu_enable(PMU_DMA); ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL); /* disable all interrupts */ ltq_dma_w32(0, LTQ_DMA_IRNEN); /* reset/configure each channel */ for (i = 0; i < DMA_MAX_CHANNEL; i++) { ltq_dma_w32(i, LTQ_DMA_CS); ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL); ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL); ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); } return 0; }
static inline void init_pmu(void) { //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9)); //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE); /* PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE); PPE_TC_PMU_SETUP(IFX_PMU_ENABLE); PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE); //PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE); PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE); DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);*/ ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 | IFX_PMU_MODULE_PPE_TC | IFX_PMU_MODULE_PPE_EMA | IFX_PMU_MODULE_TPE | IFX_PMU_MODULE_DSL_DFE); }