static void __init
luan_setup_hoses(void)
{
struct pci_controller *hose0, *hose1, *hose2;
/* Configure windows on the PCI-X host bridge */
luan_setup_pcix();
/* Allocate hoses for PCIX0, PCIX1 and PCIX2 */
hose0 = pcibios_alloc_controller();
hose1 = pcibios_alloc_controller();
hose2 = pcibios_alloc_controller();
if (!hose0 || !hose1 || !hose2)
return;
/* Setup PCIX0 */
hose0->first_busno = 0;
hose0->last_busno = 0xff;
luan_setup_hose(hose0,
LUAN_PCIX0_LOWER_MEM,
LUAN_PCIX0_UPPER_MEM,
PCIX0_CFGA,
PCIX0_CFGD,
PCIX0_IO_BASE);
hose0->last_busno = pciauto_bus_scan(hose0, hose0->first_busno);
/* Setup PCIX1 */
hose1->first_busno = hose0->last_busno + 1;
hose1->last_busno = 0xff;
luan_setup_hose(hose1,
LUAN_PCIX1_LOWER_MEM,
LUAN_PCIX1_UPPER_MEM,
PCIX1_CFGA,
PCIX1_CFGD,
PCIX1_IO_BASE);
hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
/* Setup PCIX2 */
hose2->first_busno = hose1->last_busno + 1;
hose2->last_busno = 0xff;
luan_setup_hose(hose2,
LUAN_PCIX2_LOWER_MEM,
LUAN_PCIX2_UPPER_MEM,
PCIX2_CFGA,
PCIX2_CFGD,
PCIX2_IO_BASE);
hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = luan_map_irq;
}
static void __init
luan_setup_hoses(void)
{
struct pci_controller *hose0, *hose1, *hose2;
int last_busno = -1;
/* Configure windows on the PCI-X host bridge */
luan_setup_pcix();
/* Setup PCIX0 */
if (SDR_READ(0x01c0) & 0x20000000) {
hose0 = pcibios_alloc_controller();
if (!hose0)
return;
hose0->first_busno = 0;
hose0->last_busno = 0xff;
hose0->index = 0;
luan_setup_hose(hose0,
LUAN_PCIX0_LOWER_MEM,
LUAN_PCIX0_UPPER_MEM,
PCIX0_CFGA,
PCIX0_CFGD,
PCIX0_IO_BASE);
last_busno = hose0->last_busno =
pciauto_bus_scan(hose0, hose0->first_busno);
}
/* Setup PCIX1 */
if (SDR_READ(0x01c3) & 0x20000000) {
hose1 = pcibios_alloc_controller();
if (!hose1)
return;
hose1->first_busno = last_busno + 1;
hose1->last_busno = 0xff;
hose1->index = 1;
luan_setup_hose(hose1,
LUAN_PCIX1_LOWER_MEM,
LUAN_PCIX1_UPPER_MEM,
PCIX1_CFGA,
PCIX1_CFGD,
PCIX1_IO_BASE);
last_busno = hose1->last_busno =
pciauto_bus_scan(hose1, hose1->first_busno);
}
/* Setup PCIX2 */
if (SDR_READ(0x01c6) & 0x20000000) {
hose2 = pcibios_alloc_controller();
if (!hose2)
return;
hose2->first_busno = last_busno + 1;
hose2->last_busno = 0xff;
hose2->index = 2;
luan_setup_hose(hose2,
LUAN_PCIX2_LOWER_MEM,
LUAN_PCIX2_UPPER_MEM,
PCIX2_CFGA,
PCIX2_CFGD,
PCIX2_IO_BASE);
hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
}
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = luan_map_irq;
}