inline uint32_t get_efikamx_rev(void) { if (machine_is_efikamx()) return get_mx_rev(); else if (machine_is_efikasb()) return get_sb_rev(); }
/* * Configure the USB H1 and USB H2 IOMUX */ void setup_iomux_usb(void) { setup_iomux_usb_h1(); if (machine_is_efikasb()) setup_iomux_usb_h2(); /* USB PHY reset */ mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1); mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); /* USB HUB reset */ mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); /* WIFI EN (act low) */ mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO); mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0); /* WIFI RESET */ mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO); mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0); /* BT EN (act low) */ mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO); mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0); }
int checkboard(void) { u32 rev = get_efikamx_rev(); printf("Board: Genesi Efika MX "); if (machine_is_efikamx()) printf("Smarttop (1.%i)\n", rev & 0xf); else if (machine_is_efikasb()) printf("Smartbook\n"); return 0; }
int board_mmc_init(bd_t *bis) { int ret; /* * All Efika MX boards use eSDHC1 with a common write-protect GPIO */ imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads, ARRAY_SIZE(efikamx_sdhc1_pads)); gpio_direction_input(EFIKAMX_SDHC1_WP); /* * Smartbook and Smarttop differ on the location of eSDHC1 * carrier-detect GPIO */ if (machine_is_efikamx()) { imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]); gpio_direction_input(EFIKAMX_SDHC1_CD); } else if (machine_is_efikasb()) { imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]); gpio_direction_input(EFIKASB_SDHC1_CD); } esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); if (machine_is_efikasb()) { imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads, ARRAY_SIZE(efikasb_sdhc2_pads)); gpio_direction_input(EFIKASB_SDHC2_CD); gpio_direction_input(EFIKASB_SDHC2_WP); if (!ret) ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]); } return ret; }
static int efikamx_usb_init(void) { if (!of_machine_is_compatible("genesi,imx51-sb")) return 0; barebox_set_hostname("efikasb"); mc13xxx_register_init_callback(efikamx_power_init); gpio_direction_output(GPIO_BLUETOOTH, 0); gpio_direction_output(GPIO_WIFI_ENABLE, 1); gpio_direction_output(GPIO_WIFI_RESET, 0); gpio_direction_output(GPIO_SMSC3317_RESET, 0); gpio_direction_output(GPIO_HUB_RESET, 0); gpio_direction_output(GPIO_BACKLIGHT_POWER, 1); mdelay(10); gpio_set_value(GPIO_HUB_RESET, 1); gpio_set_value(GPIO_SMSC3317_RESET, 1); gpio_set_value(GPIO_BLUETOOTH, 1); gpio_set_value(GPIO_WIFI_RESET, 1); mxc_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__GPIO1_27); gpio_set_value(IMX_GPIO_NR(1, 27), 1); mdelay(1); mxc_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP); if (machine_is_efikasb()) { mxc_iomux_v3_setup_pad(MX51_PAD_EIM_A26__GPIO2_20); gpio_set_value(IMX_GPIO_NR(2, 20), 1); mdelay(1); mxc_iomux_v3_setup_pad(MX51_PAD_EIM_A26__USBH2_STP); } switch (bootsource_get()) { case BOOTSOURCE_MMC: of_device_enable_path("/chosen/environment-sd"); break; case BOOTSOURCE_SPI: default: of_device_enable_path("/chosen/environment-spi"); break; } return 0; }
int board_late_init(void) { setup_iomux_spi(); power_init(); setup_iomux_led(); setup_iomux_ata(); setup_iomux_usb(); if (machine_is_efikasb()) setenv("preboot", "usb reset ; setenv stdin usbkbd\0"); setup_iomux_led(); efikamx_toggle_led(EFIKAMX_LED_BLUE); return 0; }
void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) { uint32_t tmp; if (port == 0) { /* Adjust UTMI PHY frequency to 24MHz */ tmp = readl(OTG_BASE_ADDR + 0x80c); tmp = (tmp & ~0x3) | 0x01; writel(tmp, OTG_BASE_ADDR + 0x80c); } else if (port == 1) { efika_ehci_init(ehci, MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT2, IOMUX_CONFIG_ALT0); } else if ((port == 2) && machine_is_efikasb()) { efika_ehci_init(ehci, MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT1, IOMUX_CONFIG_ALT2); } if (port) mdelay(10); }
/* * Board initialization */ int board_early_init_f(void) { if (machine_is_efikasb()) { imx_iomux_v3_setup_multiple_pads(efikasb_led_pads, ARRAY_SIZE(efikasb_led_pads)); gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0); gpio_direction_output(EFIKASB_MESSAGE_LED, 1); } else if (machine_is_efikamx()) { /* * Set up GPIO directions for LEDs. * IOMUX has been done in the DCD already. * Turn the red LED on for pre-relocation code. */ gpio_direction_output(EFIKAMX_LED_BLUE, 0); gpio_direction_output(EFIKAMX_LED_GREEN, 0); gpio_direction_output(EFIKAMX_LED_RED, 1); } /* * Both these pad configurations for UART and SPI are kind of redundant * since they are the Power-On Defaults for the i.MX51. But, it seems we * should make absolutely sure that they are set up correctly. */ imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads, ARRAY_SIZE(efikamx_uart_pads)); imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads, ARRAY_SIZE(efikamx_spi_pads)); /* not technically required for U-Boot operation but do it anyway. */ gpio_direction_input(EFIKAMX_PMIC_IRQ); /* Deselect both CS for now, otherwise NOR doesn't probe properly. */ gpio_direction_output(EFIKAMX_SPI_SS0, 0); gpio_direction_output(EFIKAMX_SPI_SS1, 1); return 0; }
int board_mmc_init(bd_t *bis) { int ret; uint32_t cd = efika_mmc_cd(); /* SDHC1 is used on all revisions, setup control pins first */ mxc_request_iomux(cd, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); mxc_iomux_set_pad(cd, PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); mxc_request_iomux(MX51_PIN_GPIO1_1, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); mxc_iomux_set_pad(MX51_PIN_GPIO1_1, PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_SRE_FAST); gpio_direction_input(IOMUX_TO_GPIO(cd)); gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1)); /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */ if (machine_is_efikasb() || (machine_is_efikamx() && (get_efika_rev() < EFIKAMX_BOARD_REV_12))) { /* SDHC1 IOMUX */ mxc_request_iomux(MX51_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); mxc_iomux_set_pad(MX51_PIN_SD1_CMD, PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); mxc_request_iomux(MX51_PIN_SD1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); mxc_iomux_set_pad(MX51_PIN_SD1_CLK, PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); /* SDHC2 IOMUX */ mxc_request_iomux(MX51_PIN_SD2_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); mxc_iomux_set_pad(MX51_PIN_SD2_CMD, PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); mxc_request_iomux(MX51_PIN_SD2_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); mxc_iomux_set_pad(MX51_PIN_SD2_CLK, PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); /* SDHC2 Control lines IOMUX */ mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); mxc_iomux_set_pad(MX51_PIN_GPIO1_7, PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); mxc_request_iomux(MX51_PIN_GPIO1_8, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); mxc_iomux_set_pad(MX51_PIN_GPIO1_8, PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_SRE_FAST); gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7)); ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); if (!ret) ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]); } else { /* New boards use only SDHC1 */ /* SDHC1 IOMUX */ mxc_request_iomux(MX51_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); mxc_iomux_set_pad(MX51_PIN_SD1_CMD, PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); mxc_request_iomux(MX51_PIN_SD1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); mxc_iomux_set_pad(MX51_PIN_SD1_CLK, PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); } return ret; }