_mali_osk_errcode_t mali_pmu_power_up(struct mali_pmu_core *pmu, u32 mask)
{
_mali_osk_errcode_t err;
MALI_DEBUG_ASSERT_POINTER(pmu);
MALI_DEBUG_ASSERT(pmu->registered_cores_mask != 0 );
/* Make sure we have a valid power domain mask */
if (mask & ~pmu->registered_cores_mask) {
return _MALI_OSK_ERR_INVALID_ARGS;
}
mali_pmu_lock(pmu);
MALI_DEBUG_PRINT(4, ("Mali PMU: Power up (0x%08X)\n", mask));
pmu->active_cores_mask |= mask;
_mali_osk_pm_dev_ref_add_no_power_on();
if (!mali_pm_is_power_on()) {
/* Don't touch hardware if all of Mali is powered off. */
_mali_osk_pm_dev_ref_dec_no_power_on();
mali_pmu_unlock(pmu);
MALI_DEBUG_PRINT(4, ("Mali PMU: Skipping power up (0x%08X) since Mali is off\n", mask));
return _MALI_OSK_ERR_BUSY;
}
err = mali_pmu_power_up_internal(pmu, mask);
_mali_osk_pm_dev_ref_dec_no_power_on();
mali_pmu_unlock(pmu);
return err;
}
_mali_osk_errcode_t mali_pmu_power_up_all(struct mali_pmu_core *pmu)
{
_mali_osk_errcode_t err;
MALI_DEBUG_ASSERT_POINTER(pmu);
MALI_DEBUG_ASSERT(pmu->registered_cores_mask != 0);
mali_pmu_lock(pmu);
/* Setup the desired defaults in case we were called before mali_pmu_reset() */
mali_hw_core_register_write_relaxed(&pmu->hw_core, PMU_REG_ADDR_MGMT_INT_MASK, 0);
mali_hw_core_register_write_relaxed(&pmu->hw_core, PMU_REG_ADDR_MGMT_SW_DELAY, pmu->switch_delay);
err = mali_pmu_power_up_internal(pmu, pmu->active_cores_mask);
mali_pmu_unlock(pmu);
return err;
}
_mali_osk_errcode_t mali_pmu_reset(struct mali_pmu_core *pmu)
{
_mali_osk_errcode_t err;
u32 cores_off_mask, cores_on_mask, stat;
mali_pmu_lock(pmu);
/* Setup the desired defaults */
mali_hw_core_register_write_relaxed(&pmu->hw_core, PMU_REG_ADDR_MGMT_INT_MASK, 0);
mali_hw_core_register_write_relaxed(&pmu->hw_core, PMU_REG_ADDR_MGMT_SW_DELAY, pmu->switch_delay);
/* Get power status of cores */
stat = mali_hw_core_register_read(&pmu->hw_core, PMU_REG_ADDR_MGMT_STATUS);
cores_off_mask = pmu->registered_cores_mask & ~(stat | pmu->active_cores_mask);
cores_on_mask = pmu->registered_cores_mask & (stat & pmu->active_cores_mask);
if (0 != cores_off_mask)
{
err = mali_pmu_send_command_internal(pmu, PMU_REG_ADDR_MGMT_POWER_DOWN, cores_off_mask);
if (_MALI_OSK_ERR_OK != err) return err;
}
if (0 != cores_on_mask)
{
err = mali_pmu_send_command_internal(pmu, PMU_REG_ADDR_MGMT_POWER_UP, cores_on_mask);
if (_MALI_OSK_ERR_OK != err) return err;
}
#if defined(DEBUG)
{
stat = mali_hw_core_register_read(&pmu->hw_core, PMU_REG_ADDR_MGMT_STATUS);
stat &= pmu->registered_cores_mask;
MALI_DEBUG_ASSERT(stat == (pmu->registered_cores_mask & ~pmu->active_cores_mask));
}
#endif /* defined(DEBUG) */
mali_pmu_unlock(pmu);
return _MALI_OSK_ERR_OK;
}
