/* Additional mappings for dom0 (Not in the DTS) */
static int exynos5250_specific_mapping(struct domain *d)
{
/* Map the chip ID */
map_mmio_regions(d, paddr_to_pfn(EXYNOS5_PA_CHIPID), 1,
paddr_to_pfn(EXYNOS5_PA_CHIPID));
/* Map the PWM region */
map_mmio_regions(d, paddr_to_pfn(EXYNOS5_PA_TIMER), 2,
paddr_to_pfn(EXYNOS5_PA_TIMER));
return 0;
}
/* Additional mappings for dom0 (Not in the DTS) */
static int exynos5_specific_mapping(struct domain *d)
{
/* Map the chip ID */
map_mmio_regions(d, EXYNOS5_PA_CHIPID, EXYNOS5_PA_CHIPID + PAGE_SIZE - 1,
EXYNOS5_PA_CHIPID);
/* Map the PWM region */
map_mmio_regions(d, EXYNOS5_PA_TIMER,
EXYNOS5_PA_TIMER + (PAGE_SIZE * 2) - 1,
EXYNOS5_PA_TIMER);
return 0;
}
/* Additional mappings for dom0 (not in the DTS) */
static int omap5_specific_mapping(struct domain *d)
{
/* Map the PRM module */
map_mmio_regions(d, paddr_to_pfn(OMAP5_PRM_BASE), 2,
paddr_to_pfn(OMAP5_PRM_BASE));
/* Map the PRM_MPU */
map_mmio_regions(d, paddr_to_pfn(OMAP5_PRCM_MPU_BASE), 1,
paddr_to_pfn(OMAP5_PRCM_MPU_BASE));
/* Map the Wakeup Gen */
map_mmio_regions(d, paddr_to_pfn(OMAP5_WKUPGEN_BASE), 1,
paddr_to_pfn(OMAP5_WKUPGEN_BASE));
/* Map the on-chip SRAM */
map_mmio_regions(d, paddr_to_pfn(OMAP5_SRAM_PA), 32,
paddr_to_pfn(OMAP5_SRAM_PA));
return 0;
}
static int map_one_mmio(struct domain *d, const char *what,
unsigned long start, unsigned long end)
{
int ret;
printk("Additional MMIO %lx-%lx (%s)\n",
start, end, what);
ret = map_mmio_regions(d, start, end - start, start);
if ( ret )
printk("Failed to map %s @ %lx to dom%d\n",
what, start, d->domain_id);
return ret;
}
static int map_one_mmio(struct domain *d, const char *what,
paddr_t start, paddr_t end)
{
int ret;
printk("Additional MMIO %"PRIpaddr"-%"PRIpaddr" (%s)\n",
start, end, what);
ret = map_mmio_regions(d, start, end, start);
if ( ret )
printk("Failed to map %s @ %"PRIpaddr" to dom%d\n",
what, start, d->domain_id);
return ret;
}
