static void INLINE ks7037_update(void) { WORD value; // 0x7000 value = 0x0F; control_bank(info.prg.rom[0].max.banks_4k) ks7037_prg_7000 = prg_chip_byte_pnt(0, value << 12); // 0x8000 - 0x9000 value = ks7037.reg[6]; control_bank(info.prg.rom[0].max.banks_8k) map_prg_rom_8k(1, 0, value); prg.rom_8k[0] = prg_chip_byte_pnt(prg.rom_chip[0], mapper.rom_map_to[0] << 13); // 0xA000 value = 0xFC; control_bank(info.prg.rom[0].max.banks_4k) prg.rom_8k[1] = prg_chip_byte_pnt(prg.rom_chip[0], value << 12); // 0xB000 ks7037_prg_B000 = &prg.ram_plus_8k[1 << 12]; // 0xC000 - 0xD000 value = ks7037.reg[7]; control_bank(info.prg.rom[0].max.banks_8k) map_prg_rom_8k(1, 2, value); prg.rom_8k[2] = prg_chip_byte_pnt(prg.rom_chip[0], mapper.rom_map_to[2] << 13); // mirroring ntbl.bank_1k[0] = &ntbl.data[(ks7037.reg[2] & 0x01) * 0x400]; ntbl.bank_1k[1] = &ntbl.data[(ks7037.reg[4] & 0x01) * 0x400]; ntbl.bank_1k[2] = &ntbl.data[(ks7037.reg[3] & 0x01) * 0x400]; ntbl.bank_1k[3] = &ntbl.data[(ks7037.reg[5] & 0x01) * 0x400]; }
void extcl_cpu_wr_mem_164(WORD address, BYTE value) { switch (address & 0x7300) { case 0x5000: m164.prg = (m164.prg & 0xF0) | (value & 0x0F); value = m164.prg; control_bank(info.prg.rom.max.banks_32k) map_prg_rom_8k(4, 0, value); map_prg_rom_8k_update(); return; case 0x5100: m164.prg = (m164.prg & 0x0F) | (value << 4); value = m164.prg; control_bank(info.prg.rom.max.banks_32k) map_prg_rom_8k(4, 0, value); map_prg_rom_8k_update(); return; /* case 0x5200: return; case 0x5300: value = m164.prg; control_bank(info.prg.rom.max.banks_32k) map_prg_rom_8k(4, 0, value); map_prg_rom_8k_update(); return; */ } }
void extcl_cpu_wr_mem_BMC70IN1(WORD address, BYTE value) { if (address & 0x4000) { bmc70in1.reg[0] = address & 0x30; bmc70in1.reg[1] = address & 0x07; } else { if (address & 0x20) { mirroring_H(); } else { mirroring_V(); } if (bmc70in1_type == BMC70IN1B) { bmc70in1.reg[2] = (address & 0x03) << 3; } else { DBWORD bank; value = address & 0x07; control_bank(info.chr.rom[0].max.banks_8k) bank = value << 13; chr.bank_1k[0] = chr_chip_byte_pnt(0, bank); chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400); chr.bank_1k[2] = chr_chip_byte_pnt(0, bank | 0x0800); chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0C00); chr.bank_1k[4] = chr_chip_byte_pnt(0, bank | 0x1000); chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x1400); chr.bank_1k[6] = chr_chip_byte_pnt(0, bank | 0x1800); chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x1C00); } } switch (bmc70in1.reg[0]) { case 0x00: case 0x10: value = bmc70in1.reg[2] | bmc70in1.reg[1]; control_bank(info.prg.rom[0].max.banks_16k) map_prg_rom_8k(2, 0, value); value = bmc70in1.reg[2] | 0x07; control_bank(info.prg.rom[0].max.banks_16k) map_prg_rom_8k(2, 2, value); break; case 0x20: value = (bmc70in1.reg[2] | bmc70in1.reg[1]) >> 1; control_bank(info.prg.rom[0].max.banks_32k) map_prg_rom_8k(4, 0, value); break; case 0x30: value = bmc70in1.reg[2] | bmc70in1.reg[1]; control_bank(info.prg.rom[0].max.banks_16k) map_prg_rom_8k(2, 0, value); map_prg_rom_8k(2, 2, value); break; } map_prg_rom_8k_update(); }
void extcl_cpu_wr_mem_Bandai_FCGX(WORD address, BYTE value) { if (address < 0x6000) { return; } if (!info.prg.ram.banks_8k_plus) { address |= 0x8000; } switch (address & 0x800F) { case 0x8000: case 0x8001: case 0x8002: case 0x8003: case 0x8004: case 0x8005: case 0x8006: case 0x8007: { const BYTE slot = address & 0x000F; if (info.prg.rom[0].banks_16k >= 32) { BYTE i; FCGX.reg[slot] = value; value = 0; for (i = 0; i < 8; i++) { value |= (FCGX.reg[i] << 4) & 0x10; } value |= ((mapper.rom_map_to[0] >> 1) & 0x0F); control_bank(info.prg.rom[0].max.banks_16k) map_prg_rom_8k(2, 0, value); value |= 0x0F; control_bank(info.prg.rom[0].max.banks_16k) map_prg_rom_8k(2, 2, value); map_prg_rom_8k_update(); value = FCGX.reg[slot]; } if (type == DATACH) { datach_set_scl((value << 2) & 0x20); } if (!mapper.write_vram) { control_bank(info.chr.rom[0].max.banks_1k) chr.bank_1k[slot] = chr_chip_byte_pnt(0, value << 10); } return; } case 0x8008: if (info.prg.rom[0].banks_16k >= 32) { value = ((mapper.rom_map_to[0] >> 1) & 0x10) | (value & 0x0F); }
void extcl_cpu_wr_mem_91(WORD address, BYTE value) { if (address < 0x6000) { return; } if (address <= 0x6FFF) { DBWORD bank; control_bank(info.chr.rom[0].max.banks_2k) bank = value << 11; switch (address & 0x0003) { case 0: chr.bank_1k[0] = chr_chip_byte_pnt(0, bank); chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400); return; case 1: chr.bank_1k[2] = chr_chip_byte_pnt(0, bank); chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0400); return; case 2: chr.bank_1k[4] = chr_chip_byte_pnt(0, bank); chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x0400); return; case 3: chr.bank_1k[6] = chr_chip_byte_pnt(0, bank); chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x0400); return; } } if (address < 0x7FFF) { switch (address & 0x0003) { case 0: control_bank(info.prg.rom[0].max.banks_8k) map_prg_rom_8k(1, 0, value); map_prg_rom_8k_update(); return; case 1: control_bank(info.prg.rom[0].max.banks_8k) map_prg_rom_8k(1, 1, value); map_prg_rom_8k_update(); return; case 2: m91.irq.active = 0; m91.irq.count = 0; irq.high &= ~EXT_IRQ; return; case 3: m91.irq.active = 1; irq.high &= ~EXT_IRQ; return; } } }
void extcl_cpu_wr_mem_Irem_H3000(WORD address, BYTE value) { switch (address & 0xF000) { case 0x8000: control_bank(info.prg.rom[0].max.banks_8k) map_prg_rom_8k(1, 0, value); map_prg_rom_8k_update(); break; case 0x9000: { switch (address & 0x0007) { case 1: if (value & 0x80) { mirroring_H(); } else { mirroring_V(); } break; case 3: irem_H3000.enable = value & 0x80; irq.high &= ~EXT_IRQ; break; case 4: irem_H3000.count = irem_H3000.reload; irq.high &= ~EXT_IRQ; break; case 5: irem_H3000.reload = (irem_H3000.reload & 0x00FF) | (value << 8); break; case 6: irem_H3000.reload = (irem_H3000.reload & 0xFF00) | value; break; } break; } case 0xB000: control_bank(info.chr.rom[0].max.banks_1k) chr.bank_1k[address & 0x0007] = chr_chip_byte_pnt(0, value << 10); break; case 0xA000: control_bank(info.prg.rom[0].max.banks_8k) map_prg_rom_8k(1, 1, value); map_prg_rom_8k_update(); break; case 0xC000: control_bank(info.prg.rom[0].max.banks_8k) map_prg_rom_8k(1, 2, value); map_prg_rom_8k_update(); break; } }
void extcl_cpu_wr_mem_74x161x161x32(WORD address, BYTE value) { /* bus conflict */ const BYTE save = value &= prg_rom_rd(address); DBWORD bank; if (type == IC74X161X161X32B) { if (value & 0x80) { mirroring_SCR1(); } else { mirroring_SCR0(); } } control_bank_with_AND(0x0F, info.chr.rom[0].max.banks_8k) bank = value << 13; chr.bank_1k[0] = chr_chip_byte_pnt(0, bank); chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400); chr.bank_1k[2] = chr_chip_byte_pnt(0, bank | 0x0800); chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0C00); chr.bank_1k[4] = chr_chip_byte_pnt(0, bank | 0x1000); chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x1400); chr.bank_1k[6] = chr_chip_byte_pnt(0, bank | 0x1800); chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x1C00); value = save >> 4; control_bank(info.prg.rom[0].max.banks_16k) map_prg_rom_8k(2, 0, value); map_prg_rom_8k_update(); }
void map_init_Ntdec(BYTE model) { switch (model) { case ASDER: EXTCL_CPU_WR_MEM(Ntdec_asder); EXTCL_SAVE_MAPPER(Ntdec_asder); mapper.internal_struct[0] = (BYTE *) &asder; mapper.internal_struct_size[0] = sizeof(asder); if (info.reset >= HARD) { memset(&asder, 0x00, sizeof(asder)); } break; case FHERO: EXTCL_CPU_WR_MEM(Ntdec_fhero); info.mapper.extend_wr = TRUE; if (info.reset >= HARD) { map_prg_rom_8k(4, 0, info.prg.rom.max.banks_32k); } break; } mirroring_V(); }
void map_init_Magic(void) { EXTCL_CPU_WR_MEM(Magic); if (info.reset >= HARD) { map_prg_rom_8k(4, 0, 0); } }
void extcl_cpu_wr_mem_Irem_G101(WORD address, BYTE value) { if (address >= 0xC000) { return; } switch (address & 0xF000) { case 0x8000: irem_G101.prg_reg = value; irem_G101_prg_rom_update(); break; case 0x9000: if (info.mapper.submapper != G101B) { if (value & 0x01) { mirroring_H(); } else { mirroring_V(); } } irem_G101.prg_mode = value & 0x02; value = irem_G101.prg_reg; irem_G101_prg_rom_update(); break; case 0xA000: control_bank(info.prg.rom[0].max.banks_8k) map_prg_rom_8k(1, 1, value); map_prg_rom_8k_update(); break; case 0xB000: control_bank(info.chr.rom[0].max.banks_1k) chr.bank_1k[address & 0x0007] = chr_chip_byte_pnt(0, value << 10); break; } }
void map_init_233(void) { EXTCL_CPU_WR_MEM(233); if (info.reset >= HARD) { map_prg_rom_8k(4, 0, 0); } }
void map_init_GxROM(void) { if (info.reset >= HARD) { map_prg_rom_8k(4, 0, 0); } EXTCL_CPU_WR_MEM(GxROM); }
static void INLINE bmc411120c_update_prg(void) { BYTE value; if (bmc411120c.reg & (0x08 | bmc411120c_reset)) { value = 0x0C | ((bmc411120c.reg >> 4) & 0x03); control_bank(info.prg.rom[0].max.banks_32k) map_prg_rom_8k(4, 0, value); } else {
void extcl_cpu_wr_mem_Hen_xjzb(WORD address, BYTE value) { if ((address < 0x5000) || (address > 0x5FFF)) { return; } value >>= 1; control_bank(info.prg.rom.max.banks_32k) map_prg_rom_8k(4, 0, value); map_prg_rom_8k_update(); }
void map_init_186(void) { EXTCL_CPU_WR_MEM(186); EXTCL_CPU_RD_MEM(186); EXTCL_SAVE_MAPPER(186); mapper.internal_struct[0] = (BYTE *) &m186; mapper.internal_struct_size[0] = sizeof(m186); info.mapper.extend_wr = TRUE; info.prg.ram.banks_8k_plus = 0; cpu.prg_ram_wr_active = TRUE; cpu.prg_ram_rd_active = TRUE; if (info.reset >= HARD) { memset(&m186, 0x00, sizeof(m186)); m186.prg_ram_bank2 = prg_chip(0); map_prg_rom_8k(2, 0, 0); map_prg_rom_8k(2, 2, 0); } }
void extcl_cpu_wr_mem_Bandai_161x02x74(WORD address, BYTE value) { /* bus conflict */ const BYTE save = value &= prg_rom_rd(address); DBWORD bank; control_bank_with_AND(0x03, info.prg.rom[0].max.banks_32k) map_prg_rom_8k(4, 0, value); map_prg_rom_8k_update(); b161x02x74_chr_4k_update(); }
void map_init_AxROM(void) { EXTCL_CPU_WR_MEM(AxROM); if (info.reset >= HARD) { map_prg_rom_8k(4, 0, 0); } if (info.id == BBCARUNL) { mirroring_SCR0(); } }
void map_init_Rcm(BYTE type) { switch (type) { case GS2015: EXTCL_CPU_WR_MEM(GS2015); if (info.reset >= HARD) { map_prg_rom_8k(4, 0, 0); } break; } }
void extcl_cpu_wr_mem_242(WORD address, BYTE value) { if (address & 0x0002) { mirroring_H(); } else { mirroring_V(); } value = (address & 0x0078) >> 3; control_bank(info.prg.rom.max.banks_32k) map_prg_rom_8k(4, 0, value); map_prg_rom_8k_update(); }
static void INLINE sl1632_update_mmc3(void) { WORD value; value = sl1632.mmc3.prg_map[0]; control_bank(info.prg.rom[0].max.banks_8k) map_prg_rom_8k(1, 0, value); value = sl1632.mmc3.prg_map[1]; control_bank(info.prg.rom[0].max.banks_8k) map_prg_rom_8k(1, 1, value); value = sl1632.mmc3.prg_map[2]; control_bank(info.prg.rom[0].max.banks_8k) map_prg_rom_8k(1, 2, value); value = sl1632.mmc3.prg_map[3]; control_bank(info.prg.rom[0].max.banks_8k) map_prg_rom_8k(1, 3, value); map_prg_rom_8k_update(); sl1632_update_chr_mmc3(); sl1632_mirroring(sl1632.mmc3.mirroring) }
void extcl_cpu_wr_mem_Sachen_sa0037(WORD address, BYTE value) { /* bus conflict */ const BYTE save = value &= prg_rom_rd(address); DBWORD bank; if (info.prg.rom.max.banks_32k != 0xFFFF) { value >>= 3; control_bank(info.prg.rom.max.banks_32k) map_prg_rom_8k(4, 0, value); map_prg_rom_8k_update(); value = save; }
void extcl_cpu_wr_mem_203(WORD address, BYTE value) { BYTE save = value; DBWORD bank; value = save >> 2; control_bank(info.prg.rom.max.banks_16k) map_prg_rom_8k(2, 0, value); map_prg_rom_8k(2, 2, value); map_prg_rom_8k_update(); value = save; control_bank(info.chr.rom.max.banks_8k) bank = value << 13; chr.bank_1k[0] = chr_chip_byte_pnt(0, bank); chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400); chr.bank_1k[2] = chr_chip_byte_pnt(0, bank | 0x0800); chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0C00); chr.bank_1k[4] = chr_chip_byte_pnt(0, bank | 0x1000); chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x1400); chr.bank_1k[6] = chr_chip_byte_pnt(0, bank | 0x1800); chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x1C00); }
void extcl_cpu_wr_mem_Hen_177(WORD address, BYTE value) { if (type != HEN_FANKONG) { if (value & 0x20) { mirroring_H(); } else { mirroring_V(); } } control_bank(info.prg.rom.max.banks_32k) map_prg_rom_8k(4, 0, value); map_prg_rom_8k_update(); }
void extcl_cpu_wr_mem_Ntdec_asder(WORD address, BYTE value) { switch (address & 0xE001) { case 0x8000: asder.address = value & 0x07; return; case 0xA000: { switch (asder.address) { case 0: case 1: control_bank(info.prg.rom.max.banks_8k) map_prg_rom_8k(1, asder.address, value); map_prg_rom_8k_update(); return; case 2: case 3: asder.reg[asder.address] = value >> 1; break; case 4: case 5: case 6: case 7: asder.reg[asder.address] = value; break; } break; } case 0xC000: asder.reg[0] = value; break; case 0xE000: asder.reg[1] = value; if (value & 0x01) { mirroring_H(); } else { mirroring_V(); } break; } { DBWORD bank; const WORD chr_high = (asder.reg[1] & 0x02) ? asder.reg[0] : 0; WORD new_value; asder_chr_2k_update(5, 2, 0, 1); asder_chr_2k_update(4, 3, 2, 3); asder_chr_1k_update(4, 4); asder_chr_1k_update(3, 5); asder_chr_1k_update(2, 6); asder_chr_1k_update(1, 7); } }
void extcl_cpu_wr_mem_Irem_LROG017(WORD address, BYTE value) { /* bus conflict */ const BYTE save = value &= prg_rom_rd(address); DBWORD bank; control_bank_with_AND(0x0F, info.prg.rom[0].max.banks_32k) map_prg_rom_8k(4, 0, value); map_prg_rom_8k_update(); value = save >> 4; control_bank(info.chr.rom[0].max.banks_2k) bank = value << 11; chr.bank_1k[0] = chr_chip_byte_pnt(0, bank); chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400); }
void map_init_Whirlwind(void) { EXTCL_CPU_WR_MEM(Whirlwind); EXTCL_CPU_RD_MEM(Whirlwind); EXTCL_SAVE_MAPPER(Whirlwind); mapper.internal_struct[0] = (BYTE *) &whirlwind; mapper.internal_struct_size[0] = sizeof(whirlwind); info.prg.ram.banks_8k_plus = FALSE; if (info.reset >= HARD) { memset(&whirlwind, 0x00, sizeof(whirlwind)); map_prg_rom_8k(4, 0, info.prg.rom.max.banks_32k); } }
void extcl_cpu_wr_mem_AxROM(WORD address, BYTE value) { /* bus conflict */ if (info.mapper.submapper == AMROM) { value &= prg_rom_rd(address); } if (value & 0x10) { mirroring_SCR0(); } else { mirroring_SCR1(); } control_bank_with_AND(0x0F, info.prg.rom.max.banks_32k) map_prg_rom_8k(4, 0, value); map_prg_rom_8k_update(); }
void extcl_cpu_wr_mem_57(WORD address, BYTE value) { DBWORD bank; if (address & 0x0800) { m57.reg[0] = value; if (m57.reg[0] & 0x08) { mirroring_H(); } else { mirroring_V(); } if (m57.reg[0] & 0x10) { value = (m57.reg[0] & 0xC0) >> 6; control_bank(info.prg.rom.max.banks_32k) map_prg_rom_8k(4, 0, value); } else {
void extcl_cpu_wr_mem_Ntdec_fhero(WORD address, BYTE value) { if ((address < 0x6000) || (address > 0x7FFF)) { return; } switch (address & 0x0003) { case 0: { DBWORD bank; value >>= 2; control_bank(info.chr.rom.max.banks_4k) bank = value << 12; chr.bank_1k[0] = chr_chip_byte_pnt(0, bank); chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400); chr.bank_1k[2] = chr_chip_byte_pnt(0, bank | 0x0800); chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0C00); return; } case 1: { DBWORD bank; value >>= 1; control_bank(info.chr.rom.max.banks_2k) bank = value << 11; chr.bank_1k[4] = chr_chip_byte_pnt(0, bank); chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x0400); return; } case 2: { DBWORD bank; value >>= 1; control_bank(info.chr.rom.max.banks_2k) bank = value << 11; chr.bank_1k[6] = chr_chip_byte_pnt(0, bank); chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x0400); return; } case 3: control_bank(info.prg.rom.max.banks_8k) map_prg_rom_8k(1, 0, value); map_prg_rom_8k_update(); return; } }
void map_init_Hen(BYTE model) { switch (model) { case HEN_177: case HEN_FANKONG: EXTCL_CPU_WR_MEM(Hen_177); break; case HEN_XJZB: EXTCL_CPU_WR_MEM(Hen_xjzb); info.mapper.extend_wr = TRUE; break; } if (info.reset >= HARD) { map_prg_rom_8k(4, 0, 0); } type = model; }