int mc13783_irq_status(struct mc13783 *mc13783, int irq, int *enabled, int *pending) { int ret; unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1; unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1; u32 irqbit = 1 << (irq < 24 ? irq : irq - 24); if (irq < 0 || irq >= MC13783_NUM_IRQ) return -EINVAL; if (enabled) { u32 mask; ret = mc13783_reg_read(mc13783, offmask, &mask); if (ret) return ret; *enabled = mask & irqbit; } if (pending) { u32 stat; ret = mc13783_reg_read(mc13783, offstat, &stat); if (ret) return ret; *pending = stat & irqbit; } return 0; }
int mc13783_powermisc_rmw(struct mc13783_regulator_priv *priv, u32 mask, u32 val) { struct mc13783 *mc13783 = priv->mc13783; int ret; u32 valread; BUG_ON(val & ~mask); ret = mc13783_reg_read(mc13783, MC13783_REG_POWERMISC, &valread); if (ret) return ret; /* Update the stored state for Power Gates. */ priv->powermisc_pwgt_state = (priv->powermisc_pwgt_state & ~mask) | val; priv->powermisc_pwgt_state &= MC13783_REG_POWERMISC_PWGTSPI_M; /* Construct the new register value */ valread = (valread & ~mask) | val; /* Overwrite the PWGTxEN with the stored version */ valread = (valread & ~MC13783_REG_POWERMISC_PWGTSPI_M) | priv->powermisc_pwgt_state; return mc13783_reg_write(mc13783, MC13783_REG_POWERMISC, valread); }
static int mc13783_regulator_get_voltage(struct regulator_dev *rdev) { struct mc13783_regulator_priv *priv = rdev_get_drvdata(rdev); int ret, id = rdev_get_id(rdev); unsigned int val; dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id); mc13783_lock(priv->mc13783); ret = mc13783_reg_read(priv->mc13783, mc13783_regulators[id].vsel_reg, &val); mc13783_unlock(priv->mc13783); if (ret) return ret; val = (val & mc13783_regulators[id].vsel_mask) >> mc13783_regulators[id].vsel_shift; dev_dbg(rdev_get_dev(rdev), "%s id: %d val: %d\n", __func__, id, val); BUG_ON(val < 0 || val > mc13783_regulators[id].desc.n_voltages); return mc13783_regulators[id].voltages[val]; }
static int mc13783_check_revision(struct mc13783 *mc13783) { u32 rev_id, rev1, rev2, finid, icid; mc13783_reg_read(mc13783, MC13783_REG_REVISION, &rev_id); rev1 = (rev_id & 0x018) >> 3; rev2 = (rev_id & 0x007); icid = (rev_id & 0x01C0) >> 6; finid = (rev_id & 0x01E00) >> 9; /* Ver 0.2 is actually 3.2a. Report as 3.2 */ if ((rev1 == 0) && (rev2 == 2)) rev1 = 3; if (rev1 == 0 || icid != 2) { dev_err(&mc13783->spidev->dev, "No MC13783 detected.\n"); return -ENODEV; } dev_info(&mc13783->spidev->dev, "MC13783 Rev %d.%d FinVer %x detected\n", rev1, rev2, finid); return 0; }
/* * returns: number of handled irqs or negative error * locking: holds mc13783->lock */ static int mc13783_irq_handle(struct mc13783 *mc13783, unsigned int offstat, unsigned int offmask, int baseirq) { u32 stat, mask; int ret = mc13783_reg_read(mc13783, offstat, &stat); int num_handled = 0; if (ret) return ret; ret = mc13783_reg_read(mc13783, offmask, &mask); if (ret) return ret; while (stat & ~mask) { int irq = __ffs(stat & ~mask); stat &= ~(1 << irq); if (likely(mc13783->irqhandler[baseirq + irq])) { irqreturn_t handled; handled = mc13783_irqhandler(mc13783, baseirq + irq); if (handled == IRQ_HANDLED) num_handled++; } else { dev_err(&mc13783->spidev->dev, "BUG: irq %u but no handler\n", baseirq + irq); mask |= 1 << irq; ret = mc13783_reg_write(mc13783, offmask, mask); } } return num_handled; }
static int mc13783_regulator_is_enabled(struct regulator_dev *rdev) { struct mc13783_regulator_priv *priv = rdev_get_drvdata(rdev); int ret, id = rdev_get_id(rdev); unsigned int val; mc13783_lock(priv->mc13783); ret = mc13783_reg_read(priv->mc13783, mc13783_regulators[id].reg, &val); mc13783_unlock(priv->mc13783); if (ret) return ret; return (val & mc13783_regulators[id].enable_bit) != 0; }
int mc13783_reg_rmw(struct mc13783 *mc13783, unsigned int offset, u32 mask, u32 val) { int ret; u32 valread; BUG_ON(val & ~mask); ret = mc13783_reg_read(mc13783, offset, &valread); if (ret) return ret; valread = (valread & ~mask) | val; return mc13783_reg_write(mc13783, offset, valread); }
static int mc13783_gpo_regulator_is_enabled(struct regulator_dev *rdev) { struct mc13783_regulator_priv *priv = rdev_get_drvdata(rdev); int ret, id = rdev_get_id(rdev); unsigned int val; mc13783_lock(priv->mc13783); ret = mc13783_reg_read(priv->mc13783, mc13783_regulators[id].reg, &val); mc13783_unlock(priv->mc13783); if (ret) return ret; /* Power Gates state is stored in powermisc_pwgt_state * where the meaning of bits is negated */ val = (val & ~MC13783_REG_POWERMISC_PWGTSPI_M) | (priv->powermisc_pwgt_state ^ MC13783_REG_POWERMISC_PWGTSPI_M); return (val & mc13783_regulators[id].enable_bit) != 0; }
int mc13783_irq_unmask(struct mc13783 *mc13783, int irq) { int ret; unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1; u32 irqbit = 1 << (irq < 24 ? irq : irq - 24); u32 mask; if (irq < 0 || irq >= MC13783_NUM_IRQ) return -EINVAL; ret = mc13783_reg_read(mc13783, offmask, &mask); if (ret) return ret; if (!(mask & irqbit)) /* already unmasked */ return 0; return mc13783_reg_write(mc13783, offmask, mask & ~irqbit); }
int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode, unsigned int channel, unsigned int *sample) { u32 adc0, adc1, old_adc0; int i, ret; struct mc13783_adcdone_data adcdone_data = { .mc13783 = mc13783, }; init_completion(&adcdone_data.done); dev_dbg(&mc13783->spidev->dev, "%s\n", __func__); mc13783_lock(mc13783); if (mc13783->flags & MC13783_ADC_WORKING) { ret = -EBUSY; goto out; } mc13783->flags |= MC13783_ADC_WORKING; mc13783_reg_read(mc13783, MC13783_ADC0, &old_adc0); adc0 = MC13783_ADC0_ADINC1 | MC13783_ADC0_ADINC2; adc1 = MC13783_ADC1_ADEN | MC13783_ADC1_ADTRIGIGN | MC13783_ADC1_ASC; if (channel > 7) adc1 |= MC13783_ADC1_ADSEL; switch (mode) { case MC13783_ADC_MODE_TS: adc0 |= MC13783_ADC0_ADREFEN | MC13783_ADC0_TSMOD0 | MC13783_ADC0_TSMOD1; adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT; break; case MC13783_ADC_MODE_SINGLE_CHAN: adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK; adc1 |= (channel & 0x7) << MC13783_ADC1_CHAN0_SHIFT; adc1 |= MC13783_ADC1_RAND; break; case MC13783_ADC_MODE_MULT_CHAN: adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK; adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT; break; default: mc13783_unlock(mc13783); return -EINVAL; } dev_dbg(&mc13783->spidev->dev, "%s: request irq\n", __func__); mc13783_irq_request(mc13783, MC13783_IRQ_ADCDONE, mc13783_handler_adcdone, __func__, &adcdone_data); mc13783_irq_ack(mc13783, MC13783_IRQ_ADCDONE); mc13783_reg_write(mc13783, MC13783_REG_ADC_0, adc0); mc13783_reg_write(mc13783, MC13783_REG_ADC_1, adc1); mc13783_unlock(mc13783); ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ); if (!ret) ret = -ETIMEDOUT; mc13783_lock(mc13783); mc13783_irq_free(mc13783, MC13783_IRQ_ADCDONE, &adcdone_data); if (ret > 0) for (i = 0; i < 4; ++i) { ret = mc13783_reg_read(mc13783, MC13783_REG_ADC_2, &sample[i]); if (ret) break; } if (mode == MC13783_ADC_MODE_TS) /* restore TSMOD */ mc13783_reg_write(mc13783, MC13783_REG_ADC_0, old_adc0); mc13783->flags &= ~MC13783_ADC_WORKING; out: mc13783_unlock(mc13783); return ret; }