/** * If the PLL settings are in place switch the CPU core frequency to the max. value */ static int pcm038_power_init(void) { uint32_t spctl0 = get_pll_spctl10(); struct mc13xxx *mc13xxx = mc13xxx_get(); /* PLL registers already set to their final values? */ if (spctl0 == SPCTL0_VAL && readl(MX27_CCM_BASE_ADDR + MX27_MPCTL0) == MPCTL0_VAL) { console_flush(); if (mc13xxx) { mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(0), MC13783_SWX_VOLTAGE(MC13783_SWX_VOLTAGE_1_450) | MC13783_SWX_VOLTAGE_DVS(MC13783_SWX_VOLTAGE_1_450) | MC13783_SWX_VOLTAGE_STANDBY(MC13783_SWX_VOLTAGE_1_450)); mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(4), MC13783_SW1A_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) | MC13783_SW1A_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) | MC13783_SW1A_SOFTSTART | MC13783_SW1B_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) | MC13783_SW1B_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) | MC13783_SW1B_SOFTSTART | MC13783_SW_PLL_FACTOR(32)); /* Setup VMMC voltage */ if (IS_ENABLED(CONFIG_MCI_IMX)) { u32 val; mc13xxx_reg_read(mc13xxx, MC13783_REG_REG_SETTING(1), &val); /* VMMC1 = 3.00 V */ val &= ~(7 << 6); val |= 6 << 6; mc13xxx_reg_write(mc13xxx, MC13783_REG_REG_SETTING(1), val); mc13xxx_reg_read(mc13xxx, MC13783_REG_REG_MODE(1), &val); /* Enable VMMC1 */ val |= 1 << 18; mc13xxx_reg_write(mc13xxx, MC13783_REG_REG_MODE(1), val); } /* wait for required power level to run the CPU at 400 MHz */ udelay(100000); writel(CSCR_VAL_FINAL, MX27_CCM_BASE_ADDR + MX27_CSCR); writel(0x130410c3, MX27_CCM_BASE_ADDR + MX27_PCDR0); writel(0x09030911, MX27_CCM_BASE_ADDR + MX27_PCDR1); /* Clocks have changed. Notify clients */ clock_notifier_call_chain(); } else { pr_err("Failed to initialize PMIC. Will continue with low CPU speed\n"); } } /* clock gating enable */ writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR); return 0; }
static int f3s_pmic_init(void) { struct mc13xxx *mc13xxx; struct mc9sdz60 *mc9sdz60; int rev; mc13xxx = mc13xxx_get(); if (!mc13xxx) { printf("FAILED to get PMIC handle!\n"); return 0; } rev = f3s_get_rev(mc13xxx); switch (rev) { case MX35PDK_BOARD_REV_1: break; case MX35PDK_BOARD_REV_2: f3s_pmic_init_v2(mc13xxx); break; default: printf("FAILED to identify board revision!\n"); return 0; } set_board_rev(rev); printf("i.MX35 PDK CPU board version %d.\n", rev ); mc9sdz60 = mc9sdz60_get(); if (!mc9sdz60) { printf("FAILED to get mc9sdz60 handle!\n"); return 0; } f3s_pmic_init_all(mc9sdz60); armlinux_set_revision(imx35_3ds_system_rev); return 0; }
static int loco_late_init(void) { struct mc13xxx *mc34708; int rev; if (!of_machine_is_compatible("fsl,imx53-qsb") && !of_machine_is_compatible("fsl,imx53-qsrb")) return 0; mc34708 = mc13xxx_get(); if (mc34708) { unsigned int val; int ret; /* get the board revision from fuse */ rev = readl(MX53_IIM_BASE_ADDR + 0x878); set_board_rev(rev); printf("MCIMX53-START-R board 1.0 rev %c\n", (rev == 1) ? 'A' : 'B' ); barebox_set_hostname("loco-r"); armlinux_set_revision(loco_system_rev); /* Set VDDGP to 1.25V for 1GHz on SW1 */ mc13xxx_reg_read(mc34708, MC13892_REG_SW_0, &val); val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708; ret = mc13xxx_reg_write(mc34708, MC13892_REG_SW_0, val); if (ret) { printf("Writing to REG_SW_0 failed: %d\n", ret); return ret; } /* Set VCC as 1.30V on SW2 */ mc13xxx_reg_read(mc34708, MC13892_REG_SW_1, &val); val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708; ret = mc13xxx_reg_write(mc34708, MC13892_REG_SW_1, val); if (ret) { printf("Writing to REG_SW_1 failed: %d\n", ret); return ret; } /* Set global reset timer to 4s */ mc13xxx_reg_read(mc34708, MC13892_REG_POWER_CTL2, &val); val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708; ret = mc13xxx_reg_write(mc34708, MC13892_REG_POWER_CTL2, val); if (ret) { printf("Writing to REG_POWER_CTL2 failed: %d\n", ret); return ret; } /* Set VUSBSEL and VUSBEN for USB PHY supply*/ mc13xxx_reg_read(mc34708, MC13892_REG_MODE_0, &val); val |= (VUSBSEL_MC34708 | VUSBEN_MC34708); ret = mc13xxx_reg_write(mc34708, MC13892_REG_MODE_0, val); if (ret) { printf("Writing to REG_MODE_0 failed: %d\n", ret); return ret; } /* Set SWBST to 5V in auto mode */ val = SWBST_AUTO; ret = mc13xxx_reg_write(mc34708, SWBST_CTRL, val); if (ret) { printf("Writing to SWBST_CTRL failed: %d\n", ret); return ret; } } else { /* so we have a DA9053 based board */ printf("MCIMX53-START board 1.0\n"); barebox_set_hostname("loco"); armlinux_set_revision(loco_system_rev); } /* USB PWR enable */ gpio_direction_output(MX53_LOCO_USB_PWREN, 0); gpio_set_value(MX53_LOCO_USB_PWREN, 1); loco_fec_reset(); set_silicon_rev(imx_silicon_revision()); armlinux_set_architecture(MACH_TYPE_MX53_LOCO); imx53_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0", BBU_HANDLER_FLAG_DEFAULT); return 0; }
static void babbage_power_init(void) { struct mc13xxx *mc13xxx; u32 val; mc13xxx = mc13xxx_get(); if (!mc13xxx) { printf("could not get PMIC\n"); return; } /* Write needed to Power Gate 2 register */ mc13xxx_reg_read(mc13xxx, MC13892_REG_POWER_MISC, &val); val &= ~0x10000; mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, val); /* Write needed to update Charger 0 */ mc13xxx_reg_write(mc13xxx, MC13892_REG_CHARGE, 0x0023807F); /* power up the system first */ mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, 0x00200000); if (imx_silicon_revision() < IMX_CHIP_REV_3_0) { /* Set core voltage to 1.1V */ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_0, &val); val &= ~0x1f; val |= 0x14; mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_0, val); /* Setup VCC (SW2) to 1.25 */ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val); val &= ~0x1f; val |= 0x1a; mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val); /* Setup 1V2_DIG1 (SW3) to 1.25 */ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val); val &= ~0x1f; val |= 0x1a; mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val); } else { /* Setup VCC (SW2) to 1.225 */ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val); val &= ~0x1f; val |= 0x19; mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val); /* Setup 1V2_DIG1 (SW3) to 1.2 */ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val); val &= ~0x1f; val |= 0x18; mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val); } if (mc13xxx_revision(mc13xxx) < MC13892_REVISION_2_0) { /* Set switchers in PWM mode for Atlas 2.0 and lower */ /* Setup the switcher mode for SW1 & SW2*/ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val); val &= ~0x3c0f; val |= 0x1405; mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val); /* Setup the switcher mode for SW3 & SW4 */ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val); val &= ~0xf0f; val |= 0x505; mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val); } else { /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */ /* Setup the switcher mode for SW1 & SW2*/ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val); val &= ~0x3c0f; val |= 0x2008; mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val); /* Setup the switcher mode for SW3 & SW4 */ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val); val &= ~0xf0f; val |= 0x808; mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val); } /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */ mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_0, &val); val &= ~0x34030; val |= 0x10020; mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_0, val); /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_1, &val); val &= ~0x1FC; val |= 0x1F4; mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_1, val); /* Configure VGEN3 and VCAM regulators to use external PNP */ val = 0x208; mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val); udelay(200); #define GPIO_LAN8700_RESET (1 * 32 + 14) /* Reset the ethernet controller over GPIO */ gpio_direction_output(GPIO_LAN8700_RESET, 0); /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ val = 0x49249; mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val); udelay(200); gpio_set_value(GPIO_LAN8700_RESET, 1); mdelay(50); }