int test_read_write(struct harness_t *harness_p)
{
struct canif_frame_t frame;
struct canif_frame_t frames[1];
struct mcp2515_driver_t mcp2515;
BTASSERT(mcp2515_init(&mcp2515,
&spi_device[0],
&pin_d10_dev,
&exti_device[0],
MCP2515_MODE_LOOPBACK,
MCP2515_SPEED_1000KBPS,
NULL,
frames,
membersof(frames)) == 0);
BTASSERT(mcp2515_start(&mcp2515) == 0);
/* Write a frame to the device. */
memset(&frame, 0, sizeof(frame));
frame.id = 57;
frame.data[0] = 9;
BTASSERT(mcp2515_write(&mcp2515, &frame) == 0);
/* Read a frame from the device. */
memset(&frame, 0, sizeof(frame));
BTASSERT(mcp2515_read(&mcp2515, &frame) == 0);
/* Verify frame contents. */
BTASSERT(frame.id == 57);
BTASSERT(frame.data[0] == 9);
BTASSERT(mcp2515_stop(&mcp2515) == 0);
return (0);
}
void CAN_init(){
clear_bit(INTERRUPT_DDR, INTERRUPT_BIT); //Input on the interrupt pin
uint8_t value;
SPI_init(); // Initialize SPI
mcp2515_reset(); // Send reset-command
_delay_us(20);
// Self-test
value = mcp2515_read(MCP_CANSTAT);
if ((value & MODE_MASK) != MODE_CONFIG) {
puts("MCP2515 is NOT in configuration mode after reset!\n");
}
//Sets up RXBOCTRL
//RXM = 01, activate filter, only short ID
mcp2515_bit_modify(MCP_RXB0CTRL, MCP_RXB0RXM_MASK, 1 << 5);
//BUKT: 1 -> transfers to RXB1 when RXB0 is full
mcp2515_bit_modify(MCP_RXB0CTRL, MCP_RXB0BUKT_MASK, 1 << 2);
//RXB1CTRL
//RXM = 01, activate filter, only short ID
mcp2515_bit_modify(MCP_RXB1CTRL, MCP_RXB1RXM_MASK, 1 << 5);
//Set interrupt enable
//MERRE = 0 Message error interrupt
//WAKIE = 0 (We dont use sleep)
//ERRIE = 1 Error interrupt
//TX2IE = 0 Transmit 2 empty interrupt
//TX1IE = 0 Transmit 1 empty interrupt
//TX0IE = 0 Transmit 0 empty interrupt
//RX1IE = 1 Interrupt when there is data RX1
//RX0IE = 1 Interrupt when there is data RX2
mcp2515_write(MCP_CANINTE, 0b00000011);
//Filters:
//Mask for RX0
mcp2515_write(MCP_RXM0SIDH, NODE2_CANID_H_MASK >> 3);
mcp2515_bit_modify(MCP_RXM0SIDL, 0b11100000U, NODE2_CANID_H_MASK << 5);
//Mask for RX1
mcp2515_write(MCP_RXM1SIDH, NODE2_CANID_L_MASK >> 3);
mcp2515_bit_modify(MCP_RXM1SIDL, 0b11100000U, NODE2_CANID_L_MASK << 5);
//Filter 0 (RX0, goes to RX1 if RX0 is full)
mcp2515_write(MCP_RXF0SIDH, NODE2_CANID_HIGHPRIO_0 >> 3);
mcp2515_bit_modify(MCP_RXF0SIDL, 0b11100000U, NODE2_CANID_HIGHPRIO_0 << 5);
//Filter 1 (RX0, goes to RX1 if RX0 is full)
mcp2515_write(MCP_RXF1SIDH, NODE2_CANID_HIGHPRIO_1 >> 3);
mcp2515_bit_modify(MCP_RXF1SIDL, 0b11100000U, NODE2_CANID_HIGHPRIO_1 << 5);
//Filter 2 (RX1)
mcp2515_write(MCP_RXF2SIDH, NODE2_CANID_0 >> 3);
mcp2515_bit_modify(MCP_RXF2SIDL, 0b11100000U, NODE2_CANID_0 << 5);
//Filter 3 (RX1)
mcp2515_write(MCP_RXF3SIDH, NODE2_CANID_1 >> 3);
mcp2515_bit_modify(MCP_RXF3SIDL, 0b11100000U, NODE2_CANID_1 << 5);
//Filter 4 (RX1)
mcp2515_write(MCP_RXF4SIDH, NODE2_CANID_2 >> 3);
mcp2515_bit_modify(MCP_RXF4SIDL, 0b11100000U, NODE2_CANID_2 << 5);
//Filter 5 (RX1)
mcp2515_write(MCP_RXF5SIDH, NODE2_CANID_3 >> 3);
mcp2515_bit_modify(MCP_RXF5SIDL, 0b11100000U, NODE2_CANID_3 << 5);
CAN_all_int_clear();
mcp2515_bit_modify(MCP_CANCTRL, MODE_MASK, MODE_NORMAL);
}
