static int mdiobb_read(struct mii_bus *bus, int phy, int reg) { struct mdiobb_ctrl *ctrl = bus->priv; int ret, i; if (reg & MII_ADDR_C45) { reg = mdiobb_cmd_addr(ctrl, phy, reg); mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg); } else mdiobb_cmd(ctrl, MDIO_READ, phy, reg); ctrl->ops->set_mdio_dir(ctrl, 0); /* check the turnaround bit: the PHY should be driving it to zero */ if (mdiobb_get_bit(ctrl) != 0) { /* PHY didn't drive TA low -- flush any bits it * may be trying to send. */ for (i = 0; i < 32; i++) mdiobb_get_bit(ctrl); return 0xffff; } ret = mdiobb_get_num(ctrl, 16); mdiobb_get_bit(ctrl); return ret; }
u32 mdiobb_read(int phy_base, int phy, int reg) { u32 ret; /* * Get Right Phy Address */ phy = phy + phy_base; mdiobb_cmd(MDIO_READ, phy, reg); gpio_direction_input(MDIO); mdiobb_get_bit(); /* check the turnaround bit: the PHY should be driving it to zero */ if (mdiobb_get_bit() != 0) { //printk(KERN_WARNING "MDIO BAD READ FFFF from PHY(0x%x)/REG(0x%x)\n", phy, reg); } ret = mdiobb_get_num(16); return ret; }