static void __init ubnt_uap_pro_setup(void) { u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000); ath79_register_m25p80(NULL); ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_uap_pro_gpio_leds), ubnt_uap_pro_gpio_leds); ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ARRAY_SIZE(uap_pro_gpio_keys), uap_pro_gpio_keys); ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL); ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL); ath79_register_mdio(0, 0x0); mdiobus_register_board_info(uap_pro_mdio0_info, ARRAY_SIZE(uap_pro_mdio0_info)); ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); ath79_init_mac(ath79_eth0_data.mac_addr, eeprom + UAP_PRO_MAC0_OFFSET, 0); /* GMAC0 is connected to an AR8327 switch */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0x06000000; ath79_register_eth(0); }
static void __init WPJ563_setup(void) { u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); u8 *mac = (u8 *) KSEG1ADDR(0x1f02e000); ath79_register_m25p80(NULL); ath79_register_leds_gpio(-1, ARRAY_SIZE(WPJ563_leds_gpio), WPJ563_leds_gpio); ath79_register_gpio_keys_polled(-1, WPJ563_KEYS_POLL_INTERVAL, ARRAY_SIZE(WPJ563_gpio_keys), WPJ563_gpio_keys); ath79_register_usb(); ath79_register_wmac(art + WPJ563_WMAC_CALDATA_OFFSET, NULL); ath79_register_pci(); mdiobus_register_board_info(WPJ563_mdio0_info, ARRAY_SIZE(WPJ563_mdio0_info)); ath79_register_mdio(0, 0x0); ath79_init_mac(ath79_eth0_data.mac_addr, mac + WPJ563_MAC0_OFFSET, 0); ath79_init_mac(ath79_eth1_data.mac_addr, mac + WPJ563_MAC1_OFFSET, 0); /* GMAC0 is connected to an QCA8334 switch */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; ath79_eth0_data.speed = SPEED_1000; ath79_eth0_data.duplex = DUPLEX_FULL; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_register_eth(0); }
static void __init k2t_setup(void) { u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ath79_register_m25p80(NULL); ath79_register_leds_gpio(-1, ARRAY_SIZE(k2t_leds_gpio), k2t_leds_gpio); ath79_register_gpio_keys_polled(-1, K2T_KEYS_POLL_INTERVAL, ARRAY_SIZE(k2t_gpio_keys), k2t_gpio_keys); ath79_register_usb(); platform_device_register(&ath79_mdio0_device); mdiobus_register_board_info(k2t_mdio0_info, ARRAY_SIZE(k2t_mdio0_info)); ath79_init_mac(ath79_eth0_data.mac_addr, art + K2T_MAC0_OFFSET, 0); /* GMAC0 is connected to an AR8337 switch */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; ath79_eth0_data.speed = SPEED_1000; ath79_eth0_data.duplex = DUPLEX_FULL; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_register_eth(0); ath79_register_wmac_simple(); ath79_register_pci(); }
static void __init db120_vhyfi_setup(void) { u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ath79_gpio_output_select(DB120_VHYFI_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO); ath79_register_m25p80(NULL); ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_vhyfi_leds_gpio), db120_vhyfi_leds_gpio); ath79_register_gpio_keys_polled(-1, DB120_VHYFI_KEYS_POLL_INTERVAL, ARRAY_SIZE(db120_vhyfi_gpio_keys), db120_vhyfi_gpio_keys); ath79_register_usb(); ath79_register_wmac(art + DB120_VHYFI_WMAC_CALDATA_OFFSET, NULL); ap91_pci_init(art + DB120_VHYFI_PCIE_CALDATA_OFFSET, NULL); db120_vhyfi_gmac_setup(); ath79_register_mdio(0, 0x0); ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_VHYFI_MAC0_OFFSET, 0); mdiobus_register_board_info(db120_vhyfi_mdio0_info, ARRAY_SIZE(db120_vhyfi_mdio0_info)); /* GMAC0 is connected to an AR8327 switch */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0x06000000; ath79_register_eth(0); }
static void __init rb2011_setup(void) { rb2011_gpio_init(); ath79_register_m25p80(&rb2011_spi_flash_data); rb2011_nand_init(); rb2011_gmac_setup(); ath79_register_mdio(1, 0x0); ath79_register_mdio(0, 0x0); mdiobus_register_board_info(rb2011_mdio0_info, ARRAY_SIZE(rb2011_mdio0_info)); /* GMAC0 is connected to an ar8327 switch */ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0x06000000; ath79_register_eth(0); /* GMAC1 is connected to the internal switch */ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 5); ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; ath79_eth1_data.speed = SPEED_1000; ath79_eth1_data.duplex = DUPLEX_FULL; ath79_register_eth(1); }
static void __init tl_wr1041nv2_setup(void) { u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ath79_register_m25p80(&tl_wr1041nv2_flash_data); ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1041nv2_leds_gpio), tl_wr1041nv2_leds_gpio); ath79_register_gpio_keys_polled(-1, TL_WR1041NV2_KEYS_POLL_INTERVAL, ARRAY_SIZE(tl_wr1041nv2_gpio_keys), tl_wr1041nv2_gpio_keys); ath79_register_wmac(ee, mac); ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE); ath79_register_mdio(1, 0x0); ath79_register_mdio(0, 0x0); ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); mdiobus_register_board_info(db120_mdio0_info, ARRAY_SIZE(db120_mdio0_info)); /* GMAC0 is connected to an AR8327 switch */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0x06000000; ath79_register_eth(0); }
static void __init om5p_acv2_setup(void) { u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); u8 mac[6]; /* power amplifier high power, 4.2V at RFFM4203/4503 instead of 3.3 */ ath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE); ath79_gpio_output_select(OM5PACV2_GPIO_PA_DCDC, QCA955X_GPIO_OUT_GPIO); ath79_gpio_output_select(OM5PACV2_GPIO_PA_HIGH, QCA955X_GPIO_OUT_GPIO); gpio_request_one(OM5PACV2_GPIO_PA_DCDC, GPIOF_OUT_INIT_HIGH, "PA DC/DC"); gpio_request_one(OM5PACV2_GPIO_PA_HIGH, GPIOF_OUT_INIT_HIGH, "PA HIGH"); /* temperature sensor */ platform_device_register(&om5pacv2_i2c_device); i2c_register_board_info(0, om5pacv2_i2c_devs, ARRAY_SIZE(om5pacv2_i2c_devs)); ath79_register_m25p80(&om5pacv2_flash_data); ath79_register_leds_gpio(-1, ARRAY_SIZE(om5pacv2_leds_gpio), om5pacv2_leds_gpio); ath79_register_gpio_keys_polled(-1, OM5PACV2_KEYS_POLL_INTERVAL, ARRAY_SIZE(om5pacv2_gpio_keys), om5pacv2_gpio_keys); ath79_init_mac(mac, art, 0x02); ath79_register_wmac(art + OM5PACV2_WMAC_CALDATA_OFFSET, mac); om5p_acv2_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 2, 2, 0, 0); ath79_register_mdio(0, 0x0); ath79_register_mdio(1, 0x0); mdiobus_register_board_info(om5pacv2_an_mdio0_info, ARRAY_SIZE(om5pacv2_an_mdio0_info)); ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00); ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01); /* GMAC0 is connected to the PHY4 */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_data.phy_mask = BIT(4); ath79_eth0_pll_data.pll_1000 = 0x82000101; ath79_eth0_pll_data.pll_100 = 0x80000101; ath79_eth0_pll_data.pll_10 = 0x80001313; ath79_register_eth(0); /* GMAC1 is connected to MDIO1 in SGMII mode */ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev; ath79_eth1_data.phy_mask = BIT(1); ath79_eth1_pll_data.pll_1000 = 0x03000101; ath79_eth1_pll_data.pll_100 = 0x80000101; ath79_eth1_pll_data.pll_10 = 0x80001313; ath79_eth1_data.speed = SPEED_1000; ath79_eth1_data.duplex = DUPLEX_FULL; ath79_register_eth(1); ath79_register_pci(); }
static void __init wndr4300_setup(void) { ath79_register_leds_gpio(-1, ARRAY_SIZE(wndr4300_leds_gpio), wndr4300_leds_gpio); ath79_register_gpio_keys_polled(-1, WNDR4300_KEYS_POLL_INTERVAL, ARRAY_SIZE(wndr4300_gpio_keys), wndr4300_gpio_keys); ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); mdiobus_register_board_info(wndr4300_mdio0_info, ARRAY_SIZE(wndr4300_mdio0_info)); ath79_register_mdio(0, 0x0); /* GMAC0 is connected to an AR8327N switch */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0x06000000; ath79_register_eth(0); ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW); ath79_register_nfc(); ath79_register_usb(); ath79_register_wmac_simple(); ap91_pci_init_simple(); }
static void __init cf_e385ac_setup(void) { u8 *mac = (u8 *) KSEG1ADDR(0x1f040000); cf_e38xac_common_setup(0x40000); ath79_register_leds_gpio(-1, ARRAY_SIZE(cf_e385ac_leds_gpio), cf_e385ac_leds_gpio); mdiobus_register_board_info(cf_e385ac_mdio0_info, ARRAY_SIZE(cf_e385ac_mdio0_info)); ath79_register_mdio(0, 0x0); ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); /* QCA9558 GMAC0 is connected to RMGII interface */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0x96000000; ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); ath79_register_eth(0); /* QCA9558 GMAC1 is connected to SGMII interface */ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; ath79_eth1_data.speed = SPEED_1000; ath79_eth1_data.duplex = DUPLEX_FULL; ath79_eth1_pll_data.pll_1000 = 0x03000101; ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); ath79_register_eth(1); }
static void __init dr344_setup(void) { u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); u8 *mac = (u8 *) KSEG1ADDR(0x1f03f810); ath79_register_m25p80(NULL); ath79_gpio_direction_select(DR344_GPIO_LED_STATUS, true); gpio_set_value(DR344_GPIO_LED_STATUS, 1); ath79_gpio_output_select(DR344_GPIO_LED_STATUS, 0); ath79_gpio_direction_select(DR344_GPIO_LED_LAN, true); gpio_set_value(DR344_GPIO_LED_LAN, 1); ath79_gpio_output_select(DR344_GPIO_LED_LAN, 0); ath79_register_leds_gpio(-1, ARRAY_SIZE(dr344_leds_gpio), dr344_leds_gpio); ath79_register_gpio_keys_polled(-1, DR344_KEYS_POLL_INTERVAL, ARRAY_SIZE(dr344_gpio_keys), dr344_gpio_keys); ath79_register_usb(); ath79_wmac_set_ext_lna_gpio(0, DR344_GPIO_EXTERNAL_LNA0); ath79_wmac_set_ext_lna_gpio(1, DR344_GPIO_EXTERNAL_LNA1); ath79_register_wmac(art + DR344_WMAC_CALDATA_OFFSET, NULL); ath79_register_pci(); mdiobus_register_board_info(dr344_mdio0_info, ARRAY_SIZE(dr344_mdio0_info)); ath79_register_mdio(1, 0x0); ath79_register_mdio(0, 0x0); ath79_init_mac(ath79_eth0_data.mac_addr, mac + DR344_MAC0_OFFSET, 0); ath79_init_mac(ath79_eth1_data.mac_addr, mac + DR344_MAC1_OFFSET, 0); ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE); /* GMAC0 is connected to an AR8035 Gbps PHY */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0x02000000; ath79_eth0_pll_data.pll_100 = 0x0101; ath79_eth0_pll_data.pll_10 = 0x1313; /* GMAC1 is connected to the internal switch */ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; ath79_eth1_data.speed = SPEED_1000; ath79_eth1_data.duplex = DUPLEX_FULL; ath79_register_eth(0); ath79_register_eth(1); }
static int __init rb2011_setup(u32 flags) { const struct rb_info *info; char buf[64]; info = rb_init_info((void *) KSEG1ADDR(0x1f000000), 0x10000); if (!info) return -ENODEV; scnprintf(buf, sizeof(buf), "Mikrotik RouterBOARD %s", (info->board_name) ? info->board_name : ""); mips_set_machine_name(buf); rb2011_init_partitions(info); ath79_register_m25p80(&rb2011_spi_flash_data); rb2011_nand_init(); ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE); ath79_register_mdio(1, 0x0); ath79_register_mdio(0, 0x0); mdiobus_register_board_info(rb2011_mdio0_info, ARRAY_SIZE(rb2011_mdio0_info)); /* GMAC0 is connected to an ar8327 switch */ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0x06000000; ath79_register_eth(0); /* GMAC1 is connected to the internal switch */ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 5); ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; ath79_eth1_data.speed = SPEED_1000; ath79_eth1_data.duplex = DUPLEX_FULL; ath79_register_eth(1); if (flags & RB2011_FLAG_SFP) rb2011_sfp_init(); if (flags & RB2011_FLAG_WLAN) rb2011_wlan_init(); if (flags & RB2011_FLAG_USB) ath79_register_usb(); return 0; }
static void __init esr900_setup(void) { const char *config = (char *) KSEG1ADDR(ESR900_CONFIG_ADDR); u8 *art = (u8 *) KSEG1ADDR(ESR900_CALDATA_ADDR); u8 lan_mac[ETH_ALEN]; u8 wlan0_mac[ETH_ALEN]; u8 wlan1_mac[ETH_ALEN]; if (ath79_nvram_parse_mac_addr(config, ESR900_CONFIG_SIZE, "ethaddr=", lan_mac) == 0) { ath79_init_local_mac(ath79_eth0_data.mac_addr, lan_mac); ath79_init_mac(wlan0_mac, lan_mac, 0); ath79_init_mac(wlan1_mac, lan_mac, 1); } else { pr_err("could not find ethaddr in u-boot environment\n"); } ath79_register_m25p80(NULL); ath79_register_leds_gpio(-1, ARRAY_SIZE(esr900_leds_gpio), esr900_leds_gpio); ath79_register_gpio_keys_polled(-1, ESR900_KEYS_POLL_INTERVAL, ARRAY_SIZE(esr900_gpio_keys), esr900_gpio_keys); ath79_register_usb(); ath79_register_wmac(art + ESR900_WMAC_CALDATA_OFFSET, wlan0_mac); ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); ath79_register_mdio(0, 0x0); mdiobus_register_board_info(esr900_mdio0_info, ARRAY_SIZE(esr900_mdio0_info)); /* GMAC0 is connected to the RMGII interface */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = ESR900_LAN_PHYMASK; ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0xa6000000; ath79_register_eth(0); /* GMAC1 is connected to the SGMII interface */ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; ath79_eth1_data.speed = SPEED_1000; ath79_eth1_data.duplex = DUPLEX_FULL; ath79_eth1_pll_data.pll_1000 = 0x03000101; ath79_register_eth(1); ap91_pci_init(art + ESR900_PCIE_CALDATA_OFFSET, wlan1_mac); }
static void __init common_setup(bool pcie_slot) { u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); ath79_register_m25p80(&archer_c7_flash_data); ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_leds_gpio), archer_c7_leds_gpio); ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL, ARRAY_SIZE(archer_c7_gpio_keys), archer_c7_gpio_keys); tplink_register_builtin_wmac1(ARCHER_C7_WMAC_CALDATA_OFFSET, mac, -1); if (pcie_slot) { ath79_register_pci(); } else { ap9x_pci_setup_wmac_led_pin(0, 0); tplink_register_ap91_wmac2(ARCHER_C7_PCIE_CALDATA_OFFSET, mac, 2); } mdiobus_register_board_info(archer_c7_mdio0_info, ARRAY_SIZE(archer_c7_mdio0_info)); ath79_register_mdio(0, 0x0); ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); /* GMAC0 is connected to the RMGII interface */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0x56000000; ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); ath79_register_eth(0); /* GMAC1 is connected to the SGMII interface */ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; ath79_eth1_data.speed = SPEED_1000; ath79_eth1_data.duplex = DUPLEX_FULL; ath79_eth1_pll_data.pll_1000 = 0x03000101; ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); ath79_register_eth(1); gpio_request_one(ARCHER_C7_GPIO_USB1_POWER, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, "USB1 power"); gpio_request_one(ARCHER_C7_GPIO_USB2_POWER, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, "USB2 power"); ath79_register_usb(); }
static void __init wdr7500_setup(void) { u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ath79_register_m25p80(&wdr7500_flash_data); ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr7500_leds_gpio), wdr7500_leds_gpio); ath79_register_gpio_keys_polled(-1, WDR7500_KEYS_POLL_INTERVAL, ARRAY_SIZE(wdr7500_gpio_keys), wdr7500_gpio_keys); gpio_request_one(WDR7500_GPIO_USB1_POWER, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, "USB1 power"); gpio_request_one(WDR7500_GPIO_USB2_POWER, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, "USB2 power"); ath79_register_usb(); ath79_register_nfc(); ath79_register_wmac(art + WDR7500_WMAC_CALDATA_OFFSET, NULL); ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); ath79_register_mdio(0, 0x0); ath79_init_mac(ath79_eth0_data.mac_addr, art + WDR7500_MAC0_OFFSET, 0); mdiobus_register_board_info(wdr7500_mdio0_info, ARRAY_SIZE(wdr7500_mdio0_info)); /* GMAC0 is connected to the RMGII interface */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0x56000000; ath79_register_eth(0); /* GMAC1 is connected to the SGMII interface */ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; ath79_eth1_data.speed = SPEED_1000; ath79_eth1_data.duplex = DUPLEX_FULL; ath79_eth1_pll_data.pll_1000 = 0x03000101; ath79_register_eth(1); ath79_register_pci(); }
static void __init apv5_setup(void) { u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); //ath79_gpio_output_select(APV5_GPIO_LED_STATUS, AR934X_GPIO_OUT_GPIO); //ath79_gpio_output_select(APV5_GPIO_LED_WLAN_5G, AR934X_GPIO_OUT_GPIO); ath79_gpio_output_select(APV5_GPIO_LED_WLAN_2G, AR934X_GPIO_OUT_GPIO); ath79_register_m25p80(NULL); ath79_register_leds_gpio(-1, ARRAY_SIZE(apv5_leds_gpio), apv5_leds_gpio); ath79_register_gpio_keys_polled(-1, APV5_KEYS_POLL_INTERVAL, ARRAY_SIZE(apv5_gpio_keys), apv5_gpio_keys); ath79_register_usb(); //ath79_register_wmac(art + APV5_WMAC_CALDATA_OFFSET, NULL); ath79_register_wmac(art + APV5_WMAC_CALDATA_OFFSET, NULL); memcpy(art_for_qca98xx, art + APV5_QCA98XX_CALDATA_OFFSET, sizeof(art_for_qca98xx)); //zhaoyang1 modifies for loading qca98xx cal data 2015-02-06 ap91_pci_init(art + APV5_PCIE_CALDATA_OFFSET, NULL); ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE); ath79_register_mdio(1, 0x0); ath79_register_mdio(0, 0x0); ath79_init_mac(ath79_eth0_data.mac_addr, art + APV5_MAC0_OFFSET, 0); mdiobus_register_board_info(apv5_mdio0_info, ARRAY_SIZE(apv5_mdio0_info)); /* GMAC0 is connected to an AR8327 switch */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0x06000000; ath79_register_eth(0); #if 0 /* GMAC1 is connected to the internal switch */ ath79_init_mac(ath79_eth1_data.mac_addr, art + APV5_MAC1_OFFSET, 0); ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; ath79_eth1_data.speed = SPEED_1000; ath79_eth1_data.duplex = DUPLEX_FULL; ath79_register_eth(1); #endif ath79_register_nfc(); }
static void __init archer_c7_setup(void) { u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); u8 tmpmac[ETH_ALEN]; ath79_register_m25p80(&archer_c7_flash_data); ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_leds_gpio), archer_c7_leds_gpio); ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL, ARRAY_SIZE(archer_c7_gpio_keys), archer_c7_gpio_keys); ath79_init_mac(tmpmac, mac, -1); ath79_register_wmac(art + ARCHER_C7_WMAC_CALDATA_OFFSET, tmpmac); ath79_register_pci(); mdiobus_register_board_info(archer_c7_mdio0_info, ARRAY_SIZE(archer_c7_mdio0_info)); ath79_register_mdio(0, 0x0); archer_c7_gmac_setup(); /* GMAC0 is connected to the RMGII interface */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0x56000000; ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); ath79_register_eth(0); /* GMAC1 is connected to the SGMII interface */ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; ath79_eth1_data.speed = SPEED_1000; ath79_eth1_data.duplex = DUPLEX_FULL; ath79_eth1_pll_data.pll_1000 = 0x03000101; ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); ath79_register_eth(1); gpio_request_one(ARCHER_C7_GPIO_USB1_POWER, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, "USB1 power"); gpio_request_one(ARCHER_C7_GPIO_USB2_POWER, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, "USB2 power"); ath79_register_usb(); }
static void __init om5p_an_setup(void) { u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); u8 mac[6]; /* temperature sensor */ platform_device_register(&om5pan_i2c_device); i2c_register_board_info(0, om5pan_i2c_devs, ARRAY_SIZE(om5pan_i2c_devs)); /* make lan / wan leds software controllable */ ath79_gpio_output_select(OM5P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO); ath79_gpio_output_select(OM5P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO); ath79_register_m25p80(&om5p_flash_data); ath79_register_leds_gpio(-1, ARRAY_SIZE(om5p_leds_gpio), om5p_leds_gpio); ath79_init_mac(mac, art, 0x02); ath79_register_wmac(art + OM5P_WMAC_CALDATA_OFFSET, mac); ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); ath79_setup_ar934x_eth_rx_delay(2, 2); ath79_register_mdio(0, 0x0); ath79_register_mdio(1, 0x0); mdiobus_register_board_info(om5p_an_mdio0_info, ARRAY_SIZE(om5p_an_mdio0_info)); ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00); ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01); /* GMAC0 is connected to the PHY7 */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_data.phy_mask = BIT(7); ath79_eth0_pll_data.pll_1000 = 0x02000000; ath79_eth0_pll_data.pll_100 = 0x00000101; ath79_eth0_pll_data.pll_10 = 0x00001313; ath79_register_eth(0); /* GMAC1 is connected to the internal switch */ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev; ath79_register_eth(1); ath79_init_mac(mac, art, 0x10); ap91_pci_init(art + OM5P_PCI_CALDATA_OFFSET, mac); }
static void __init wdr4300_setup(void) { u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); u8 tmpmac[ETH_ALEN]; ath79_register_m25p80(&wdr4300_flash_data); ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr4300_leds_gpio), wdr4300_leds_gpio); ath79_register_gpio_keys_polled(-1, WDR4300_KEYS_POLL_INTERVAL, ARRAY_SIZE(wdr4300_gpio_keys), wdr4300_gpio_keys); ath79_wmac_set_ext_lna_gpio(0, WDR4300_GPIO_EXTERNAL_LNA0); ath79_wmac_set_ext_lna_gpio(1, WDR4300_GPIO_EXTERNAL_LNA1); ath79_init_mac(tmpmac, mac, -1); ath79_register_wmac(art + WDR4300_WMAC_CALDATA_OFFSET, tmpmac); ath79_init_mac(tmpmac, mac, 0); ap9x_pci_setup_wmac_led_pin(0, 0); ap91_pci_init(art + WDR4300_PCIE_CALDATA_OFFSET, tmpmac); ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); mdiobus_register_board_info(wdr4300_mdio0_info, ARRAY_SIZE(wdr4300_mdio0_info)); ath79_register_mdio(0, 0x0); ath79_init_mac(ath79_eth0_data.mac_addr, mac, -2); /* GMAC0 is connected to an AR8327N switch */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0x06000000; ath79_register_eth(0); gpio_request_one(WDR4300_GPIO_USB1_POWER, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, "USB1 power"); gpio_request_one(WDR4300_GPIO_USB2_POWER, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, "USB2 power"); ath79_register_usb(); }
static void __init rb922gs_setup(void) { const struct rb_info *info; char buf[64]; info = rb_init_info((void *) KSEG1ADDR(0x1f000000), 0x10000); if (!info) return; scnprintf(buf, sizeof(buf), "Mikrotik RouterBOARD %s", (info->board_name) ? info->board_name : ""); mips_set_machine_name(buf); rb922gs_init_partitions(info); ath79_register_m25p80(&rb922gs_spi_flash_data); rb922gs_nand_init(); ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); ath79_register_mdio(0, 0x0); mdiobus_register_board_info(rb922gs_mdio0_info, ARRAY_SIZE(rb922gs_mdio0_info)); ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(RB922_PHY_ADDR); ath79_eth0_pll_data.pll_10 = 0x81001313; ath79_eth0_pll_data.pll_100 = 0x81000101; ath79_eth0_pll_data.pll_1000 = 0x8f000000; ath79_register_eth(0); ath79_register_pci(); ath79_register_leds_gpio(-1, ARRAY_SIZE(rb922gs_leds), rb922gs_leds); ath79_register_gpio_keys_polled(-1, RB922_KEYS_POLL_INTERVAL, ARRAY_SIZE(rb922gs_gpio_keys), rb922gs_gpio_keys); /* NOTE: * This only supports the RB911G-5HPacD board for now. For other boards * more devices must be registered based on the hardware options which * can be found in the hardware configuration of RouterBOOT. */ }
static void __init dir825c1_setup(void) { u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000); u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); u8 tmpmac[ETH_ALEN]; u8 mac1[ETH_ALEN], mac2[ETH_ALEN]; dir825c1_read_ascii_mac(mac1, mac + DIR825C1_MAC0_OFFSET); dir825c1_read_ascii_mac(mac2, mac + DIR825C1_MAC1_OFFSET); ath79_gpio_output_select(DIR825C1_GPIO_LED_BLUE_USB, AR934X_GPIO_OUT_GPIO); ath79_register_m25p80(NULL); ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825c1_leds_gpio), dir825c1_leds_gpio); ath79_register_gpio_keys_polled(-1, DIR825C1_KEYS_POLL_INTERVAL, ARRAY_SIZE(dir825c1_gpio_keys), dir825c1_gpio_keys); ap9x_pci_setup_wmac_led_pin(0, 13); ap9x_pci_setup_wmac_led_pin(1, 32); ath79_init_mac(tmpmac, mac1, 0); ath79_register_wmac(art + DIR825C1_WMAC_CALDATA_OFFSET, tmpmac); ath79_init_mac(tmpmac, mac2, 0); ap91_pci_init(art + DIR825C1_PCIE_CALDATA_OFFSET, tmpmac); ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); mdiobus_register_board_info(dir825c1_mdio0_info, ARRAY_SIZE(dir825c1_mdio0_info)); ath79_register_mdio(0, 0x0); ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); /* GMAC0 is connected to an AR8327N switch */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0x06000000; ath79_register_eth(0); ath79_register_usb(); }
/* * Init the hAP ac / 962UiGS-5HacT2HnT hardware (QCA9558). * The hAP ac has 5 ethernet ports provided by an AR8337 switch. Port 1 is * assigned to WAN, ports 2-5 are assigned to LAN. Port 0 is connected to the * SoC, ports 1-5 of the switch are connected to physical ports 1-5 in order. * The SFP cage is not assigned by default on RouterOS. Extra work is required * to support this interface as it is directly connected to the SoC (eth1). * Wireless is provided by a 2.4GHz radio on the SoC (WLAN1) and a 5GHz radio * attached via PCI (QCA9880). Red and green WLAN LEDs are populated however * they are not attached to GPIOs, extra work is required to support these. * PoE and USB output power control is supported. */ static void __init rb962_setup(void) { u32 flags = RBSPI_HAS_USB | RBSPI_HAS_POE | RBSPI_HAS_PCI; if (!rbspi_platform_setup()) return; rbspi_peripherals_setup(flags); /* Do not call rbspi_network_setup as we have a discrete switch chip */ ath79_eth0_pll_data.pll_1000 = 0xae000000; ath79_eth0_pll_data.pll_100 = 0xa0000101; ath79_eth0_pll_data.pll_10 = 0xa0001313; ath79_register_mdio(0, 0x0); mdiobus_register_board_info(rb962_mdio0_info, ARRAY_SIZE(rb962_mdio0_info)); ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_register_eth(0); /* WLAN1 MAC is HW MAC + 7 */ rbspi_wlan_init(1, 7); if (flags & RBSPI_HAS_USB) gpio_request_one(RB962_GPIO_USB_PWROFF, GPIOF_ACTIVE_LOW | GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, "USB power off"); /* PoE output GPIO is inverted, set GPIOF_ACTIVE_LOW for consistency */ if (flags & RBSPI_HAS_POE) gpio_request_one(RB962_GPIO_POE_POWER, GPIOF_OUT_INIT_HIGH | GPIOF_ACTIVE_LOW | GPIOF_EXPORT_DIR_FIXED, "POE power"); ath79_register_leds_gpio(-1, ARRAY_SIZE(rb962_leds_gpio), rb962_leds_gpio); /* This device has a single reset button as gpio 20 */ rbspi_register_reset_button(RB962_GPIO_BTN_RESET); }
static void __init dlan_pro_1200_ac_setup(void) { u8 *art = (u8 *) KSEG1ADDR(DLAN_PRO_1200_AC_ART_ADDRESS); u8 *cal = art + DLAN_PRO_1200_AC_CALDATA_OFFSET; u8 *wifi_mac = art + DLAN_PRO_1200_AC_WIFIMAC_OFFSET; ath79_register_m25p80(NULL); ath79_register_leds_gpio(-1, ARRAY_SIZE(dlan_pro_1200_ac_leds_gpio), dlan_pro_1200_ac_leds_gpio); ath79_register_gpio_keys_polled(-1, DLAN_PRO_1200_AC_KEYS_POLL_INTERVAL, ARRAY_SIZE(dlan_pro_1200_ac_gpio_keys), dlan_pro_1200_ac_gpio_keys); /* dLAN power must be enabled from user-space as soon as the boot-from-host daemon is running */ gpio_request_one(DLAN_PRO_1200_AC_GPIO_DLAN_POWER_ENABLE, GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED, "dLAN power"); /* WLAN power is turned on initially to allow the PCI bus scan to succeed */ gpio_request_one(DLAN_PRO_1200_AC_GPIO_WLAN_POWER_ENABLE, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, "WLAN power"); ath79_register_wmac(cal, wifi_mac); ap91_pci_init(art + DLAN_PRO_1200_AC_PCIE_CALDATA_OFFSET, NULL); ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE); ath79_register_mdio(1, 0x0); ath79_register_mdio(0, 0x0); ath79_init_mac(ath79_eth0_data.mac_addr, wifi_mac, 2); mdiobus_register_board_info(dlan_pro_1200_ac_mdio0_info, ARRAY_SIZE(dlan_pro_1200_ac_mdio0_info)); /* GMAC0 is connected to an AR8337 */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0x02000000; ath79_register_eth(0); }
static void __init dw33d_setup(void) { u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ath79_register_m25p80(NULL); ath79_register_leds_gpio(-1, ARRAY_SIZE(dw33d_leds_gpio), dw33d_leds_gpio); ath79_register_gpio_keys_polled(-1, DW33D_KEYS_POLL_INTERVAL, ARRAY_SIZE(dw33d_gpio_keys), dw33d_gpio_keys); ath79_register_usb(); ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW); ath79_register_nfc(); ath79_register_pci(); ath79_register_wmac(art + DW33D_WMAC_CALDATA_OFFSET, art + DW33D_WMAC_OFFSET); ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); ath79_register_mdio(0, 0x0); ath79_init_mac(ath79_eth0_data.mac_addr, art + DW33D_MAC0_OFFSET, 0); ath79_init_mac(ath79_eth1_data.mac_addr, art + DW33D_MAC1_OFFSET, 0); mdiobus_register_board_info(dw33d_mdio0_info, ARRAY_SIZE(dw33d_mdio0_info)); /* GMAC0 is connected to the RMGII interface */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0x56000000; ath79_register_eth(0); /* GMAC1 is connected tot eh SGMII interface */ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; ath79_eth1_data.speed = SPEED_1000; ath79_eth1_data.duplex = DUPLEX_FULL; ath79_eth1_pll_data.pll_1000 = 0x03000101; ath79_register_eth(1); }
void __init orion_ge00_switch_init(struct dsa_chip_data *d) { struct mdio_board_info *bd; unsigned int i; for (i = 0; i < ARRAY_SIZE(d->port_names); i++) if (!strcmp(d->port_names[i], "cpu")) break; bd = &orion_ge00_switch_board_info; bd->bus_id = orion_ge00_mvmdio_bus_name; bd->mdio_addr = d->sw_addr; d->netdev[i] = &orion_ge00.dev; strcpy(bd->modalias, "mv88e6085"); bd->platform_data = d; mdiobus_register_board_info(&orion_ge00_switch_board_info, 1); }
static void __init tl_wr1043nd_v2_setup(void) { u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); ath79_register_m25p80(&wr1043nd_v2_flash_data); ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1043_v2_leds_gpio), tl_wr1043_v2_leds_gpio); ath79_register_gpio_keys_polled(-1, TL_WR1043_V2_KEYS_POLL_INTERVAL, ARRAY_SIZE(tl_wr1043_v2_gpio_keys), tl_wr1043_v2_gpio_keys); tplink_register_builtin_wmac1(TL_WR1043_V2_WMAC_CALDATA_OFFSET, mac, -1); mdiobus_register_board_info(wr1043nd_v2_mdio0_info, ARRAY_SIZE(wr1043nd_v2_mdio0_info)); ath79_register_mdio(0, 0x0); ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); /* GMAC0 is connected to the RMGII interface */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0x56000000; ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); ath79_register_eth(0); /* GMAC1 is connected to the SGMII interface */ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; ath79_eth1_data.speed = SPEED_1000; ath79_eth1_data.duplex = DUPLEX_FULL; ath79_eth1_pll_data.pll_1000 = 0x03000101; ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); ath79_register_eth(1); ath79_register_usb(); gpio_request_one(TL_WR1043_V2_GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, "USB power"); }
static void __init mr900_setup(void) { u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); u8 mac[6], pcie_mac[6]; struct ath9k_platform_data *pdata; ath79_eth0_pll_data.pll_1000 = 0xae000000; ath79_eth0_pll_data.pll_100 = 0xa0000101; ath79_eth0_pll_data.pll_10 = 0xa0001313; ath79_register_m25p80(NULL); ath79_register_leds_gpio(-1, ARRAY_SIZE(mr900_leds_gpio), mr900_leds_gpio); ath79_register_gpio_keys_polled(-1, MR900_KEYS_POLL_INTERVAL, ARRAY_SIZE(mr900_gpio_keys), mr900_gpio_keys); ath79_init_mac(mac, art + MR900_MAC0_OFFSET, 1); ath79_register_wmac(art + MR900_WMAC_CALDATA_OFFSET, mac); ath79_init_mac(pcie_mac, art + MR900_MAC0_OFFSET, 16); ap91_pci_init(art + MR900_PCIE_CALDATA_OFFSET, pcie_mac); pdata = ap9x_pci_get_wmac_data(0); if (!pdata) { pr_err("mr900: unable to get address of wlan data\n"); return; } pdata->use_eeprom = true; mr900_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0); ath79_register_mdio(0, 0x0); mdiobus_register_board_info(mr900_mdio0_info, ARRAY_SIZE(mr900_mdio0_info)); ath79_init_mac(ath79_eth0_data.mac_addr, art + MR900_MAC0_OFFSET, 0); /* GMAC0 is connected to the RMGII interface */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(5); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_register_eth(0); }
static void __init mynet_n750_setup(void) { u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); u8 tmpmac[ETH_ALEN]; ath79_register_m25p80(NULL); ath79_register_leds_gpio(-1, ARRAY_SIZE(mynet_n750_leds_gpio), mynet_n750_leds_gpio); ath79_register_gpio_keys_polled(-1, MYNET_N750_KEYS_POLL_INTERVAL, ARRAY_SIZE(mynet_n750_gpio_keys), mynet_n750_gpio_keys); /* * Control signal for external LNAs 0 and 1 * Taken from GPL bootloader source: * board/ar7240/db12x/alpha_gpio.c */ ath79_wmac_set_ext_lna_gpio(0, MYNET_N750_GPIO_EXTERNAL_LNA0); ath79_wmac_set_ext_lna_gpio(1, MYNET_N750_GPIO_EXTERNAL_LNA1); mynet_n750_get_mac("wlan24mac=", tmpmac); ath79_register_wmac(art + MYNET_N750_WMAC_CALDATA_OFFSET, tmpmac); mynet_n750_get_mac("wlan5mac=", tmpmac); ap91_pci_init(art + MYNET_N750_PCIE_CALDATA_OFFSET, tmpmac); ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); mdiobus_register_board_info(mynet_n750_mdio0_info, ARRAY_SIZE(mynet_n750_mdio0_info)); ath79_mdio0_data.reset = mynet_n750_mdio_fixup; ath79_register_mdio(0, 0x0); mynet_n750_get_mac("lanmac=", ath79_eth0_data.mac_addr); /* GMAC0 is connected to an AR8327N switch */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0x06000000; ath79_register_eth(0); ath79_register_usb(); }
void __init orion_ge00_switch_init(struct dsa_chip_data *d) { unsigned int i; if (!IS_BUILTIN(CONFIG_PHYLIB)) return; for (i = 0; i < ARRAY_SIZE(d->port_names); i++) { if (!strcmp(d->port_names[i], "cpu")) { d->netdev[i] = &orion_ge00.dev; break; } } orion_ge00_switch_board_info.mdio_addr = d->sw_addr; orion_ge00_switch_board_info.platform_data = d; mdiobus_register_board_info(&orion_ge00_switch_board_info, 1); }
static void __init rb95x_setup(void) { rb95x_gpio_init(); rb95x_nand_init(); ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE); ath79_register_mdio(0, 0x0); mdiobus_register_board_info(rb95x_mdio0_info, ARRAY_SIZE(rb95x_mdio0_info)); ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_register_eth(0); }
static void __init wpj344_setup(void) { u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ath79_register_m25p80(NULL); ath79_register_leds_gpio(-1, ARRAY_SIZE(wpj344_leds_gpio), wpj344_leds_gpio); ath79_register_gpio_keys_polled(-1, WPJ344_KEYS_POLL_INTERVAL, ARRAY_SIZE(wpj344_gpio_keys), wpj344_gpio_keys); ath79_register_usb(); ath79_register_wmac(art + WPJ344_WMAC_CALDATA_OFFSET, NULL); ath79_register_pci(); mdiobus_register_board_info(wpj344_mdio0_info, ARRAY_SIZE(wpj344_mdio0_info)); ath79_register_mdio(1, 0x0); ath79_register_mdio(0, 0x0); ath79_init_mac(ath79_eth0_data.mac_addr, art + WPJ344_MAC0_OFFSET, 0); ath79_init_mac(ath79_eth1_data.mac_addr, art + WPJ344_MAC1_OFFSET, 0); ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE); /* GMAC0 is connected to an AR8327 switch */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ath79_eth0_pll_data.pll_1000 = 0x06000000; /* GMAC1 is connected to the internal switch */ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; ath79_eth1_data.speed = SPEED_1000; ath79_eth1_data.duplex = DUPLEX_FULL; ath79_register_eth(0); ath79_register_eth(1); }