void mdp4_overlay_lcdc_vsync_push(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe)
{
unsigned long flag;
if (pipe->flags & MDP_OV_PLAY_NOWAIT)
return;
if (lcdc_pipe->blt_addr) {
mdp4_overlay_lcdc_dma_busy_wait(mfd);
mdp4_lcdc_blt_ov_update(lcdc_pipe);
lcdc_pipe->ov_cnt++;
spin_lock_irqsave(&mdp_spin_lock, flag);
outp32(MDP_INTR_CLEAR, INTR_OVERLAY0_DONE);
mdp_intr_mask |= INTR_OVERLAY0_DONE;
outp32(MDP_INTR_ENABLE, mdp_intr_mask);
mdp_enable_irq(MDP_OVERLAY0_TERM);
mfd->dma->busy = TRUE;
mb(); /* make sure all registers updated */
spin_unlock_irqrestore(&mdp_spin_lock, flag);
outpdw(MDP_BASE + 0x0004, 0); /* kickoff overlay engine */
mdp4_stat.kickoff_ov0++;
mb();
mdp4_overlay_lcdc_wait4event(mfd, INTR_DMA_P_DONE);
} else {
mdp4_overlay_lcdc_wait4event(mfd, INTR_PRIMARY_VSYNC);
}
mdp4_set_perf_level();
}
static void mdp4_overlay_lcdc_prefill(struct msm_fb_data_type *mfd)
{
unsigned long flag;
if (lcdc_pipe->ov_blt_addr) {
mdp4_overlay_lcdc_dma_busy_wait(mfd);
mdp4_lcdc_blt_ov_update(lcdc_pipe);
lcdc_pipe->ov_cnt++;
spin_lock_irqsave(&mdp_spin_lock, flag);
outp32(MDP_INTR_CLEAR, INTR_OVERLAY0_DONE);
mdp_intr_mask |= INTR_OVERLAY0_DONE;
outp32(MDP_INTR_ENABLE, mdp_intr_mask);
mdp_enable_irq(MDP_OVERLAY0_TERM);
mfd->dma->busy = TRUE;
mb(); /* make sure all registers updated */
spin_unlock_irqrestore(&mdp_spin_lock, flag);
outpdw(MDP_BASE + 0x0004, 0); /* kickoff overlay engine */
mdp4_stat.kickoff_ov0++;
mb();
}
}
