static void sis_85c501_recalcmapping(void)
{
int c, d;
for (c = 0; c < 1; c++)
{
for (d = 0; d < 4; d++)
{
uint32_t base = 0xe0000 + (d << 14);
if (sis_85c501.pci_conf[0x54 + c] & (1 << (d + 4)))
{
switch (sis_85c501.pci_conf[0x53] & 0x60)
{
case 0x00:
mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
case 0x20:
mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 0x40:
mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
case 0x60:
mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
}
}
else
mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
}
}
flushmmucache();
shadowbios = 1;
}
void headland_write(uint16_t addr, uint8_t val, void *priv)
{
if (addr & 1)
{
if (headland_index == 0xc1 && !is486) val = 0;
headland_regs[headland_index] = val;
pclog("Headland write %02X %02X\n",headland_index,val);
if (headland_index == 0x82)
{
shadowbios = val & 0x10;
shadowbios_write = !(val & 0x10);
if (shadowbios)
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
else
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
}
}
else
headland_index = val;
}