//====================================================
// enables/disables cache
//====================================================
void caching(Xuint8 Enable) {
	if (Enable) {
		  /*
		 * Enable and initialize cache
		 */
		#if XPAR_MICROBLAZE_0_USE_ICACHE
			xil_printf("Enabling and initializing instruction cache\r\n");
			microblaze_enable_icache();
		#endif
	
		#if XPAR_MICROBLAZE_0_USE_DCACHE	
			xil_printf("Enabling and initializing data cache\r\n");	
			microblaze_enable_dcache();
		#endif
	} else {
		#if XPAR_MICROBLAZE_0_USE_DCACHE
			xil_printf("Disabling data cache\r\n");
			microblaze_disable_dcache();
		#endif
	
		#if XPAR_MICROBLAZE_0_USE_ICACHE
			xil_printf("Disabling instruction cache\r\n");
			microblaze_disable_icache();
		#endif
	}
}
Пример #2
0
int main() {
    proc_interface_t hwti;
	 
    // Get HWTI base address from user PVR register
    int hwti_base;
    getpvr(1,hwti_base);

    // Disable instruction and data cache
    microblaze_invalidate_icache();
    microblaze_disable_icache();
    microblaze_invalidate_dcache();
	 microblaze_disable_dcache();
    // Nano-kernel loop...
    while(1) {
        // Setup interface
		// * Perform this upon each iteration, just in case the memory
		//   map for the MB-HWTI is corrupted.
	    initialize_interface(&hwti,(int*)(hwti_base));

#if 0   // Commented out as this is not necessary and it creates the opportunity for a race between reset and start commands
        // Wait to be "reset"
		// -- NOTE: Ignore reset as it has no meaning to the MB-HWTI
		//          and it seems causes a race, as the controlling processor
		//          sends a reset, immediately followed by a "go" command.  Therefore
		//          the "reset" command can be missed.
	    wait_for_reset_command(&hwti);
        
#endif

	    // Wait to be "started"
	    wait_for_go_command(&hwti);

		//xil_printf("Thread started (fcn @ 0x%08x), arg = 0x%08x!!!\r\n",*(hwti.fcn_reg), *(hwti.arg_reg));

        // Setup r20 for thread, this can be used to enforce -fPIC (Position-independent code) for the MB
        // (r20 is used as part of the GOT, to make things PC-relative)
        mtgpr(r20, *(hwti.fcn_reg));

        // Boostrap thread (wraps up thread execution with a thread exit)
        //  * Pull out thread argument, and thread start function
        _bootstrap_thread(&hwti, *(hwti.fcn_reg), *(hwti.arg_reg));
		 
    }
    return 0;
}
void
disable_caches()
{
#ifdef __PPC__
    XCache_DisableDCache();
    XCache_DisableICache();
#elif __MICROBLAZE__
#ifdef XPAR_MICROBLAZE_USE_DCACHE
#if !XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
    microblaze_invalidate_dcache();
#endif
    microblaze_disable_dcache();
#endif
#ifdef XPAR_MICROBLAZE_USE_ICACHE
    microblaze_invalidate_icache();
    microblaze_disable_icache();
#endif
#endif
}
int main(void)
{
	int Status;

   /*
    * Enable and initialize cache
    */
#if !SIM

   #if XPAR_MICROBLAZE_0_USE_ICACHE
      microblaze_invalidate_icache();
      microblaze_enable_icache();
   #endif

   #if XPAR_MICROBLAZE_0_USE_DCACHE
      microblaze_invalidate_dcache();
       microblaze_enable_dcache();
   #endif
#endif


	XUartNs550_SetBaud(UART_BASEADDR, UART_CLOCK, UART_BAUDRATE);
	XUartNs550_SetLineControlReg(UART_BASEADDR, XUN_LCR_8_DATA_BITS);


  xil_printf("\n\r********************************************************");
  xil_printf("\n\r********************************************************");
  xil_printf("\n\r**     SP605 - Temac Test                             **");
  xil_printf("\n\r********************************************************");
  xil_printf("\n\r********************************************************\r\n");

	printf("Setting Temac and DMA\r\n");
    printf("\r\n");

	/*
	 * Call the Temac SGDMA interrupt example , specify the parameters generated
	 * in xparameters.h
	 */
	Status = TemacSgDmaIntrExample(&IntcInstance,
				       &TemacInstance,
				       &DmaInstance,
				       TEMAC_DEVICE_ID,
				       TEMAC_IRPT_INTR,
				       DMA_RX_IRPT_INTR, DMA_TX_IRPT_INTR);
	if (Status != XST_SUCCESS) {
		TemacUtilErrorTrap("Failure in Examples");
		return XST_FAILURE;
	}

    printf("Received Packet!\r\n");
    printf("\r\n");

#if !SIM

   #if XPAR_MICROBLAZE_0_USE_DCACHE
      microblaze_disable_dcache();
      microblaze_invalidate_dcache();
   #endif

   #if XPAR_MICROBLAZE_0_USE_ICACHE
      microblaze_disable_icache();
      microblaze_invalidate_icache();
   #endif
#endif

	return_to_loader();

	return 0;

}
Пример #5
0
int main (void) {


   static XIntc intc;

   /*
    * Enable and initialize cache
    */
   #if XPAR_MICROBLAZE_0_USE_ICACHE
      microblaze_init_icache_range(0, XPAR_MICROBLAZE_0_CACHE_BYTE_SIZE);
      microblaze_enable_icache();
   #endif

   #if XPAR_MICROBLAZE_0_USE_DCACHE
      microblaze_init_dcache_range(0, XPAR_MICROBLAZE_0_DCACHE_BYTE_SIZE);
      microblaze_enable_dcache();
   #endif

   static XEmacLite Ethernet_MAC_EmacLite;
   print("-- Entering main() --\r\n");


   {
      XStatus status;
      
      print("\r\n Runnning IntcSelfTestExample() for xps_intc_0...\r\n");
      
      status = IntcSelfTestExample(XPAR_XPS_INTC_0_DEVICE_ID);
      
      if (status == 0) {
         print("IntcSelfTestExample PASSED\r\n");
      }
      else {
         print("IntcSelfTestExample FAILED\r\n");
      }
   } 
	
   {
       XStatus Status;

       Status = IntcInterruptSetup(&intc, XPAR_XPS_INTC_0_DEVICE_ID);
       if (Status == 0) {
          print("Intc Interrupt Setup PASSED\r\n");
       } 
       else {
         print("Intc Interrupt Setup FAILED\r\n");
      } 
   }

   /*
    * Peripheral SelfTest will not be run for RS232_Uart_1
    * because it has been selected as the STDOUT device
    */



   {
      Xuint32 status;
      
      print("\r\nRunning GpioOutputExample() for LEDs_8Bit...\r\n");

      status = GpioOutputExample(XPAR_LEDS_8BIT_DEVICE_ID,8);
      
      if (status == 0) {
         print("GpioOutputExample PASSED.\r\n");
      }
      else {
         print("GpioOutputExample FAILED.\r\n");
      }
   }


   {
      XStatus status;
      
      print("\r\nRunning EMACLiteSelfTestExample() for Ethernet_MAC...\r\n");
      status = EMACLiteSelfTestExample(XPAR_ETHERNET_MAC_DEVICE_ID);
      if (status == 0) {
         print("EMACLiteSelfTestExample PASSED\r\n");
      }
      else {
         print("EMACLiteSelfTestExample FAILED\r\n");
      }
   }
   {
      XStatus Status;

      print("\r\n Running Interrupt Test  for Ethernet_MAC...\r\n");
      
      Status = EmacLiteExample(&intc, &Ethernet_MAC_EmacLite, \
                               XPAR_ETHERNET_MAC_DEVICE_ID, \
                               XPAR_XPS_INTC_0_ETHERNET_MAC_IP2INTC_IRPT_INTR);
	
      if (Status == 0) {
         print("EmacLite Interrupt Test PASSED\r\n");
      } 
      else {
         print("EmacLite Interrupt Test FAILED\r\n");
      }

   }


   {
      XStatus status;
      
      print("\r\n Running TmrCtrSelfTestExample() for xps_timer_1...\r\n");
      
      status = TmrCtrSelfTestExample(XPAR_XPS_TIMER_1_DEVICE_ID, 0x0);
      
      if (status == 0) {
         print("TmrCtrSelfTestExample PASSED\r\n");
      }
      else {
         print("TmrCtrSelfTestExample FAILED\r\n");
      }
   }


   {
      XStatus status;
      
      print("\r\nRunning UartLiteSelfTestExample() for debug_module...\r\n");
      status = UartLiteSelfTestExample(XPAR_DEBUG_MODULE_DEVICE_ID);
      if (status == 0) {
         print("UartLiteSelfTestExample PASSED\r\n");
      }
      else {
         print("UartLiteSelfTestExample FAILED\r\n");
      }
   }
   /*
    * Disable cache and reinitialize it so that other
    * applications can be run with no problems
    */
   #if XPAR_MICROBLAZE_0_USE_DCACHE
      microblaze_disable_dcache();
      microblaze_init_dcache_range(0, XPAR_MICROBLAZE_0_DCACHE_BYTE_SIZE);
   #endif

   #if XPAR_MICROBLAZE_0_USE_ICACHE
      microblaze_disable_icache();
      microblaze_init_icache_range(0, XPAR_MICROBLAZE_0_CACHE_BYTE_SIZE);
   #endif


   print("-- Exiting main() --\r\n");
   return 0;
}