/*
* Read an PHY register through the MII.
*/
static int
vr_mii_readreg(device_t self, int phy, int reg)
{
struct vr_softc *sc = device_private(self);
CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
return (mii_bitbang_readreg(self, &vr_mii_bitbang_ops, phy, reg));
}
int
dl10019_mii_readreg(struct device *self, int phy, int reg)
{
struct ne2000_softc *nsc = (void *) self;
const struct mii_bitbang_ops *ops;
ops = (nsc->sc_type == NE2000_TYPE_DL10022) ?
&dl10022_mii_bitbang_ops : &dl10019_mii_bitbang_ops;
return (mii_bitbang_readreg(self, ops, phy, reg));
}
/*
* MII bus support routines.
*/
static int
ed_miibus_readreg(device_t dev, int phy, int reg)
{
struct ed_softc *sc;
int val;
uint8_t cr = 0;
sc = device_get_softc(dev);
/*
* The AX88790 has an interesting quirk. It has an internal phy that
* needs a special bit set to access, but can also have additional
* external PHYs set for things like HomeNET media. When accessing
* the internal PHY, a bit has to be set, when accessing the external
* PHYs, it must be clear. See Errata 1, page 51, in the AX88790
* datasheet for more details.
*
* Also, PHYs above 16 appear to be phantoms on some cards, but not
* others. Registers read for this are often the same as prior values
* read. Filter all register requests to 17-31.
*/
if (sc->chip_type == ED_CHIP_TYPE_AX88790) {
if (phy > 0x10)
return (0);
if (phy == 0x10)
ed_asic_outb(sc, ED_AX88X90_GPIO,
ED_AX88X90_GPIO_INT_PHY);
else
ed_asic_outb(sc, ED_AX88X90_GPIO, 0);
ed_asic_barrier(sc, ED_AX88X90_GPIO, 1,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
} else if (sc->chip_type == ED_CHIP_TYPE_TC5299J) {
/* Select page 3. */
ed_nic_barrier(sc, ED_P0_CR, 1,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
cr = ed_nic_inb(sc, ED_P0_CR);
ed_nic_outb(sc, ED_P0_CR, cr | ED_CR_PAGE_3);
ed_nic_barrier(sc, ED_P0_CR, 1,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
}
val = mii_bitbang_readreg(dev, sc->mii_bitbang_ops, phy, reg);
if (sc->chip_type == ED_CHIP_TYPE_TC5299J) {
/* Restore prior page. */
ed_nic_outb(sc, ED_P0_CR, cr);
ed_nic_barrier(sc, ED_P0_CR, 1,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
}
return (val);
}
int
bmac_mii_readreg(struct device *dev, int phy, int reg)
{
return mii_bitbang_readreg(dev, &bmac_mbo, phy, reg);
}
static int
ax88190_mii_readreg(device_t self, int phy, int reg)
{
return (mii_bitbang_readreg(self, &ax88190_mii_bitbang_ops, phy, reg));
}
