void __mii_init(void) { FEC_INFO_T *info; volatile FEC_T *fecp; struct eth_device *dev; int miispd = 0, i = 0; u16 status = 0; u16 linkgood = 0; /* retrieve from register structure */ dev = eth_get_dev(); info = dev->priv; fecp = (FEC_T *) info->miibase; fecpin_setclear(dev, 1); mii_reset(info); /* We use strictly polling mode only */ fecp->eimr = 0; /* Clear any pending interrupt */ fecp->eir = 0xffffffff; /* Set MII speed */ miispd = (gd->bus_clk / 1000000) / 5; fecp->mscr = miispd << 1; info->phy_addr = mii_discover_phy(dev); while (i < MCFFEC_TOUT_LOOP) { status = 0; i++; /* Read PHY control register */ miiphy_read(dev->name, info->phy_addr, MII_BMCR, &status); /* If phy set to autonegotiate, wait for autonegotiation done, * if phy is not autonegotiating, just wait for link up. */ if ((status & BMCR_ANENABLE) == BMCR_ANENABLE) { linkgood = (BMSR_ANEGCOMPLETE | BMSR_LSTATUS); } else { linkgood = BMSR_LSTATUS; } /* Read PHY status register */ miiphy_read(dev->name, info->phy_addr, MII_BMSR, &status); if ((status & linkgood) == linkgood) break; udelay(1); } if (i >= MCFFEC_TOUT_LOOP) { printf("Link UP timeout\n"); } /* adapt to the duplex and speed settings of the phy */ info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); }
void __mii_init(void) { volatile fec_t *fecp; struct fec_info_s *info; struct eth_device *dev; int miispd = 0, i = 0; u16 autoneg = 0; /* retrieve from register structure */ dev = eth_get_dev(); info = dev->priv; fecp = (fec_t *) info->miibase; fecpin_setclear(dev, 1); mii_reset(info); /* We use strictly polling mode only */ fecp->eimr = 0; /* Clear any pending interrupt */ fecp->eir = 0xffffffff; /* Set MII speed */ miispd = (gd->bus_clk / 1000000) / 5; fecp->mscr = miispd << 1; info->phy_addr = mii_discover_phy(dev); #define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) while (i < MCFFEC_TOUT_LOOP) { autoneg = 0; miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); i++; if ((autoneg & AUTONEGLINK) == AUTONEGLINK) break; udelay(500); } if (i >= MCFFEC_TOUT_LOOP) { printf("Auto Negotiation not complete\n"); } /* adapt to the half/full speed settings */ info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); }
static int fec_init(struct eth_device* dev, bd_t *bis) { struct ether_fcc_info_s * info = dev->priv; int i; volatile immap_t *immr = (immap_t *)CFG_IMMR; volatile ccsr_cpm_cp_t *cp = &(immr->im_cpm.im_cpm_cp); fcc_enet_t *pram_ptr; unsigned long mem_addr; #if 0 mii_discover_phy(); #endif /* 28.9 - (1-2): ioports have been set up already */ /* 28.9 - (3): connect FCC's tx and rx clocks */ immr->im_cpm.im_cpm_mux.cmxuar = 0; /* ATM */ immr->im_cpm.im_cpm_mux.cmxfcr = (immr->im_cpm.im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) | info->cmxfcr_value; /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */ if(info->ether_index == 0) { immr->im_cpm.im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; } else if (info->ether_index == 1) { immr->im_cpm.im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; } else if (info->ether_index == 2) { immr->im_cpm.im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; } /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */ if(info->ether_index == 0) { immr->im_cpm.im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; } else if (info->ether_index == 1){ immr->im_cpm.im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; } else if (info->ether_index == 2){ immr->im_cpm.im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; } /* 28.9 - (6): FDSR: Ethernet Syn */ if(info->ether_index == 0) { immr->im_cpm.im_cpm_fcc1.fdsr = 0xD555; } else if (info->ether_index == 1) { immr->im_cpm.im_cpm_fcc2.fdsr = 0xD555; } else if (info->ether_index == 2) { immr->im_cpm.im_cpm_fcc3.fdsr = 0xD555; } /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */ rxIdx = 0; txIdx = 0; /* Setup Receiver Buffer Descriptors */ for (i = 0; i < PKTBUFSRX; i++) { rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; rtx.rxbd[i].cbd_datlen = 0; rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i]; } rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; /* Setup Ethernet Transmitter Buffer Descriptors */ for (i = 0; i < TX_BUF_CNT; i++) { rtx.txbd[i].cbd_sc = 0; rtx.txbd[i].cbd_datlen = 0; rtx.txbd[i].cbd_bufaddr = 0; } rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; /* 28.9 - (7): initialize parameter ram */ pram_ptr = (fcc_enet_t *)&(immr->im_cpm.im_dprambase[info->proff_enet]); /* clear whole structure to make sure all reserved fields are zero */ memset((void*)pram_ptr, 0, sizeof(fcc_enet_t)); /* * common Parameter RAM area * * Allocate space in the reserved FCC area of DPRAM for the * internal buffers. No one uses this space (yet), so we * can do this. Later, we will add resource management for * this area. CPM_FCC_SPECIAL_BASE: 0xb000. */ mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64); pram_ptr->fen_genfcc.fcc_riptr = mem_addr; pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32; /* * Set maximum bytes per receive buffer. * It must be a multiple of 32. */ pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */ /* localbus SDRAM should be preferred */ pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB | CFG_CPMFCR_RAMTYPE) << 24; pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]); pram_ptr->fen_genfcc.fcc_rbdstat = 0; pram_ptr->fen_genfcc.fcc_rbdlen = 0; pram_ptr->fen_genfcc.fcc_rdptr = 0; /* localbus SDRAM should be preferred */ pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB | CFG_CPMFCR_RAMTYPE) << 24; pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]); pram_ptr->fen_genfcc.fcc_tbdstat = 0; pram_ptr->fen_genfcc.fcc_tbdlen = 0; pram_ptr->fen_genfcc.fcc_tdptr = 0; /* protocol-specific area */ pram_ptr->fen_statbuf = 0x0; pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */ pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */ pram_ptr->fen_crcec = 0; pram_ptr->fen_alec = 0; pram_ptr->fen_disfc = 0; pram_ptr->fen_retlim = 15; /* Retry limit threshold */ pram_ptr->fen_retcnt = 0; pram_ptr->fen_pper = 0; pram_ptr->fen_boffcnt = 0; pram_ptr->fen_gaddrh = 0; pram_ptr->fen_gaddrl = 0; pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */ /* * Set Ethernet station address. * * This is supplied in the board information structure, so we * copy that into the controller. * So far we have only been given one Ethernet address. We make * it unique by setting a few bits in the upper byte of the * non-static part of the address. */ #define ea eth_get_dev()->enetaddr pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4]; pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2]; pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0]; #undef ea pram_ptr->fen_ibdcount = 0; pram_ptr->fen_ibdstart = 0; pram_ptr->fen_ibdend = 0; pram_ptr->fen_txlen = 0; pram_ptr->fen_iaddrh = 0; /* disable hash */ pram_ptr->fen_iaddrl = 0; pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */ /* pad pointer. use tiptr since we don't need a specific padding char */ pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr; pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length:1520 */ pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length:1520 */ #if defined(ET_DEBUG) printf("parm_ptr(0xff788500) = %p\n",pram_ptr); printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n", pram_ptr->fen_genfcc.fcc_rbase); printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n", pram_ptr->fen_genfcc.fcc_tbase); #endif /* 28.9 - (8)(9): clear out events in FCCE */ /* 28.9 - (9): FCCM: mask all events */ if(info->ether_index == 0) { immr->im_cpm.im_cpm_fcc1.fcce = ~0x0; immr->im_cpm.im_cpm_fcc1.fccm = 0; } else if (info->ether_index == 1) { immr->im_cpm.im_cpm_fcc2.fcce = ~0x0; immr->im_cpm.im_cpm_fcc2.fccm = 0; } else if (info->ether_index == 2) { immr->im_cpm.im_cpm_fcc3.fcce = ~0x0; immr->im_cpm.im_cpm_fcc3.fccm = 0; } /* 28.9 - (10-12): we don't use ethernet interrupts */ /* 28.9 - (13) * * Let's re-initialize the channel now. We have to do it later * than the manual describes because we have just now finished * the BD initialization. */ cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page, info->cpm_cr_enet_sblock, 0x0c, CPM_CR_INIT_TRX) | CPM_CR_FLG; do { __asm__ __volatile__ ("eieio"); } while (cp->cpcr & CPM_CR_FLG); /* 28.9 - (14): enable tx/rx in gfmr */ if(info->ether_index == 0) { immr->im_cpm.im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; } else if (info->ether_index == 1) { immr->im_cpm.im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; } else if (info->ether_index == 2) { immr->im_cpm.im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; } return 1; }
void __mii_init(void) { FEC_INFO_T *info; volatile FEC_T *fecp; struct eth_device *dev; int miispd = 0, i = 0; u16 status = 0; u16 linkgood = 0; /* retrieve from register structure */ dev = eth_get_dev(); info = dev->priv; fecp = (FEC_T *) info->miibase; fecpin_setclear(dev, 1); mii_reset(info); /* We use strictly polling mode only */ fecp->eimr = 0; /* Clear any pending interrupt */ fecp->eir = 0xffffffff; /* Set MII speed */ #ifdef CONFIG_M68K miispd = (gd->bus_clk / 1000000) / 5; #else /* * The MSCR[MII_SPEED] bit field is minus 1 encoded. * * We round the value in MSCR[MII_SPEED] up, so that the MDC frequency * never exceeds CONFIG_MCFFEC_MII_SPEED_LIMIT. */ miispd = (CONFIG_MCFFEC_MAC_CLK - 1) / (2 * CONFIG_MCFFEC_MII_SPEED_LIMIT); #endif /* CONFIG_M68K */ if (miispd > MCFFEC_MII_SPEED_MAX) miispd = MCFFEC_MII_SPEED_MAX; fecp->mscr = miispd << 1; info->phy_addr = mii_discover_phy(dev); while (i < MCFFEC_TOUT_LOOP) { status = 0; i++; /* Read PHY control register */ miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &status); /* If phy set to autonegotiate, wait for autonegotiation done, * if phy is not autonegotiating, just wait for link up. */ if ((status & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) { linkgood = (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS); } else { linkgood = PHY_BMSR_LS; } /* Read PHY status register */ miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &status); if ((status & linkgood) == linkgood) break; udelay(1); } if (i >= MCFFEC_TOUT_LOOP) { printf("Link UP timeout\n"); } /* adapt to the duplex and speed settings of the phy */ info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); }