void disp_ext_util_dsi_clk_off( void )
{
DISP_LOCAL_LOG_EMERG("%s start\n",__func__);
local_bh_disable();
mipi_dsi_clk_disable();
local_bh_enable();
MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0);
mipi_dsi_phy_ctrl(0);
local_bh_disable();
mipi_dsi_ahb_ctrl(0);
local_bh_enable();
DISP_LOCAL_LOG_EMERG("%s end\n",__func__);
return;
}
static int mipi_dsi_off(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
struct msm_panel_info *pinfo;
//#if defined(CONFIG_MACH_MSM8960_CHEETAH) || defined(CONFIG_MACH_MSM8960_VEGAPVW) || defined(CONFIG_MACH_MSM8960_SIRIUSLTE)|| defined(CONFIG_MACH_MSM8960_EF44S) || defined(CONFIG_MACH_MSM8960_MAGNUS)
#if defined(CONFIG_MACH_MSM8960_CHEETAH) || defined(CONFIG_MACH_MSM8960_SIRIUSLTE)|| defined(CONFIG_MACH_MSM8960_EF44S) || defined(CONFIG_MACH_MSM8960_MAGNUS)
struct mipi_panel_info *mipi;
#endif
mfd = platform_get_drvdata(pdev);
pinfo = &mfd->panel_info;
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND);
//#if defined(CONFIG_MACH_MSM8960_CHEETAH) || defined(CONFIG_MACH_MSM8960_VEGAPVW) || defined(CONFIG_MACH_MSM8960_SIRIUSLTE)|| defined(CONFIG_MACH_MSM8960_EF44S) || defined(CONFIG_MACH_MSM8960_MAGNUS)
#if defined(CONFIG_MACH_MSM8960_CHEETAH) || defined(CONFIG_MACH_MSM8960_SIRIUSLTE)|| defined(CONFIG_MACH_MSM8960_EF44S) || defined(CONFIG_MACH_MSM8960_MAGNUS)
mipi = &mfd->panel_info.mipi;
if (mipi->force_clk_lane_hs) {
u32 tmp;
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp &= ~(1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
printk("[MIPI: shinbrad Low speed Clk Set(Off Sequence) .................................................]\n");
}
#endif
/*
* Description: dsi clock is need to perform shutdown.
* mdp4_dsi_cmd_dma_busy_wait() will enable dsi clock if disabled.
* also, wait until dma (overlay and dmap) finish.
*/
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (mdp_rev >= MDP_REV_41) {
mdp4_dsi_cmd_dma_busy_wait(mfd);
mdp4_dsi_blt_dmap_busy_wait(mfd);
mipi_dsi_mdp_busy_wait(mfd);
} else {
mdp3_dsi_cmd_dma_busy_wait(mfd);
}
} else {
/* video mode, wait until fifo cleaned */
#if !defined(CONFIG_MACH_MSM8960_MAGNUS)
mipi_dsi_controller_cfg(0);
#endif
}
/*
* Desctiption: change to DSI_CMD_MODE since it needed to
* tx DCS dsiplay off comamnd to panel
*/
#if defined (CONFIG_MACH_MSM8960_MAGNUS)
ret = panel_next_off(pdev);
mipi_dsi_controller_cfg(0);
#else
mipi_dsi_op_mode_config(DSI_CMD_MODE);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (MDP_REV_303 != mdp_rev)
gpio_free(vsync_gpio);
}
mipi_dsi_set_tear_off(mfd);
}
}
ret = panel_next_off(pdev);
#endif
#ifdef CONFIG_MSM_BUS_SCALING
mdp_bus_scale_update_request(0);
#endif
local_bh_disable();
mipi_dsi_clk_disable();
local_bh_enable();
/* disbale dsi engine */
MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0);
mipi_dsi_phy_ctrl(0);
local_bh_disable();
mipi_dsi_ahb_ctrl(0);
local_bh_enable();
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(0);
if (mdp_rev >= MDP_REV_41)
mutex_unlock(&mfd->dma->ov_mutex);
else
up(&mfd->dma->mutex);
pr_debug("%s-:\n", __func__);
return ret;
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
int target_type = 0;
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
// clk struck error msg p13447 Shinjg 201205
cont_splash_clk_ctrl();
local_bh_disable();
mipi_dsi_ahb_ctrl(1);
local_bh_enable();
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi_dsi_phy_ctrl(1);
if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
local_bh_disable();
mipi_dsi_clk_enable();
local_bh_enable();
mipi = &mfd->panel_info.mipi;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.mipi.xres_pad;
dummy_yres = mfd->panel_info.mipi.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
/* DSI_LAN_SWAP_CTRL */
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3; /* Default format set to RGB888 */
ystride = width * bpp + 1;
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi);
#if 0
if (mipi->force_clk_lane_hs) {
u32 tmp;
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp |= (1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
}
#endif
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
#ifdef CONFIG_F_SKYDISP_SILENT_BOOT
if(!backlight_value)
#endif
#if 0//defined (CONFIG_MACH_MSM8960_MAGNUS)
mipi_dsi_op_mode_config(mipi->mode);
msleep(35);
ret = panel_next_on(pdev);
#else
ret = panel_next_on(pdev);
mipi_dsi_op_mode_config(mipi->mode);
#endif
//#if defined(CONFIG_MACH_MSM8960_CHEETAH) || defined(CONFIG_MACH_MSM8960_VEGAPVW) || defined(CONFIG_MACH_MSM8960_SIRIUSLTE) || defined(CONFIG_MACH_MSM8960_EF44S) || defined(CONFIG_MACH_MSM8960_MAGNUS)
#if defined(CONFIG_MACH_MSM8960_CHEETAH) || defined(CONFIG_MACH_MSM8960_SIRIUSLTE) || defined(CONFIG_MACH_MSM8960_EF44S) || defined(CONFIG_MACH_MSM8960_MAGNUS)
if (mipi->force_clk_lane_hs) {
u32 tmp;
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp |= (1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
printk("[MIPI: shinbrad High speed Clk Set .................................................]\n");
}
#endif
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (mdp_rev >= MDP_REV_41) {
if (gpio_request(vsync_gpio,
"MDP_VSYNC") == 0)
gpio_direction_input(
vsync_gpio);
else
pr_err("%s: unable to \
request gpio=%d\n",
__func__, vsync_gpio);
} else if (mdp_rev == MDP_REV_303) {
if (!tlmm_settings && gpio_request(
vsync_gpio, "MDP_VSYNC") == 0) {
ret = gpio_tlmm_config(
GPIO_CFG(
vsync_gpio, 1,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (ret) {
pr_err(
"%s: unable to config \
tlmm = %d\n",
__func__, vsync_gpio);
}
tlmm_settings = TRUE;
gpio_direction_input(
vsync_gpio);
} else {
if (!tlmm_settings) {
pr_err(
"%s: unable to request \
gpio=%d\n",
__func__, vsync_gpio);
}
}
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
int target_type = 0;
printk("%s+:\n", __func__);
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
esc_byte_ratio = pinfo->mipi.esc_byte_ratio;
if (mfd->first_init_lcd == 0) {
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
}
cont_splash_clk_ctrl(0);
mipi_dsi_prepare_clocks();
mipi_dsi_ahb_ctrl(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
mipi_dsi_phy_ctrl(1);
if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
mipi_dsi_clk_enable();
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi = &mfd->panel_info.mipi;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.lcdc.xres_pad;
dummy_yres = mfd->panel_info.lcdc.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac,
mipi_dsi_pdata->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else {
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3;
ystride = width * bpp + 1;
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi, mipi_dsi_pdata->dlane_swap);
if (mipi->force_clk_lane_hs) {
u32 tmp;
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp |= (1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
}
#if defined(CONFIG_MACH_DUMMY)
if ((panel_type == PANEL_ID_PROTODCG_SHARP || panel_type == PANEL_ID_PROTODCG_SHARP_C1) &&
mfd->first_init_lcd != 0) {
protodcg_orise_lcd_pre_off(pdev);
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
}
#elif defined(CONFIG_MACH_PROTOU)
if ((panel_type == PANEL_ID_PROTOU_SHARP || panel_type == PANEL_ID_PROTOU_SHARP_C1) &&
mfd->first_init_lcd != 0) {
protou_orise_lcd_pre_off(pdev);
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
}
#endif
if (panel_type == PANEL_ID_URANUS_SONY_ORISE) {
if(mfd->first_init_lcd != 0) {
if (mipi_dsi_pdata && mipi_dsi_pdata->lcd_pre_off)
mipi_dsi_pdata->lcd_pre_off(pdev);
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
}
}
ret = panel_next_on(pdev);
mipi_dsi_op_mode_config(mipi->mode);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (mdp_rev >= MDP_REV_41) {
if (gpio_request(vsync_gpio,
"MDP_VSYNC") == 0)
gpio_direction_input(
vsync_gpio);
else
pr_err("%s: unable to \
request gpio=%d\n",
__func__, vsync_gpio);
} else if (mdp_rev == MDP_REV_303) {
if (!tlmm_settings && gpio_request(
vsync_gpio, "MDP_VSYNC") == 0) {
ret = gpio_tlmm_config(
GPIO_CFG(
vsync_gpio, 1,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (ret) {
pr_err(
"%s: unable to config \
tlmm = %d\n",
__func__, vsync_gpio);
}
tlmm_settings = TRUE;
gpio_direction_input(
vsync_gpio);
} else {
if (!tlmm_settings) {
pr_err(
"%s: unable to request \
gpio=%d\n",
__func__, vsync_gpio);
}
}
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
int target_type = 0;
#ifdef CONFIG_HUAWEI_KERNEL
unsigned int datamask = 0;
#endif
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
local_bh_disable();
mipi_dsi_ahb_ctrl(1);
local_bh_enable();
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
/*
* It because of the reset and clock order,
* that Qualcomm baseband will be issued a special waveform,
* this cause the lcd enter the wrong state and data 0 will be pulled low,
* and mipi dsi will work abnormal.
*/
#ifdef CONFIG_HUAWEI_KERNEL
local_bh_disable();
mipi_dsi_clk_enable();
local_bh_enable();
#endif
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi_dsi_phy_ctrl(1);
if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
/*
* It because of the reset and clock order,
* that Qualcomm baseband will be issued a special waveform,
* this cause the lcd enter the wrong state and data 0 will be pulled low,
* and mipi dsi will work abnormal.
*/
#ifndef CONFIG_HUAWEI_KERNEL
local_bh_disable();
mipi_dsi_clk_enable();
local_bh_enable();
#endif
mipi = &mfd->panel_info.mipi;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.mipi.xres_pad;
dummy_yres = mfd->panel_info.mipi.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
/* DSI_LAN_SWAP_CTRL */
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3; /* Default format set to RGB888 */
ystride = width * bpp + 1;
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi);
if (mipi->force_clk_lane_hs) {
u32 tmp;
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp |= (1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
}
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
#ifdef CONFIG_HUAWEI_KERNEL
/*when here there is a wrong sequence bofore ,so add 5 ms hope lcd panel can enter the right mode */
mdelay(5);
/* request data line and clock line to exit the ulps mode */
if (mipi->data_lane3)
datamask |= 1<<11;
if (mipi->data_lane2)
datamask |= 1<<10;
if (mipi->data_lane1)
datamask |= 1<<9;
if (mipi->data_lane0)
datamask |= 1<<8;
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, datamask | (1<<12));
/* It is the mipi request ,at least 1 ms*/
mdelay(2);
/*absolutely exit the ulps mode */
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, 0);
#endif
ret = panel_next_on(pdev);
mipi_dsi_op_mode_config(mipi->mode);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (mdp_rev >= MDP_REV_41) {
if (gpio_request(vsync_gpio,
"MDP_VSYNC") == 0)
gpio_direction_input(
vsync_gpio);
else
pr_err("%s: unable to \
request gpio=%d\n",
__func__, vsync_gpio);
} else if (mdp_rev == MDP_REV_303) {
if (!tlmm_settings && gpio_request(
vsync_gpio, "MDP_VSYNC") == 0) {
ret = gpio_tlmm_config(
GPIO_CFG(
vsync_gpio, 1,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (ret) {
pr_err(
"%s: unable to config \
tlmm = %d\n",
__func__, vsync_gpio);
}
tlmm_settings = TRUE;
gpio_direction_input(
vsync_gpio);
} else {
if (!tlmm_settings) {
pr_err(
"%s: unable to request \
gpio=%d\n",
__func__, vsync_gpio);
}
}
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
int target_type = 0;
pr_debug("%s+:\n", __func__);
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
esc_byte_ratio = pinfo->mipi.esc_byte_ratio;
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
cont_splash_clk_ctrl(0);
mipi_dsi_prepare_clocks();
mipi_dsi_ahb_ctrl(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
mipi_dsi_phy_ctrl(1);
if (mdp_rev >= MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
mipi_dsi_clk_enable();
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi = &mfd->panel_info.mipi;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.lcdc.xres_pad;
dummy_yres = mfd->panel_info.lcdc.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
/* DSI_LAN_SWAP_CTRL */
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3; /* Default format set to RGB888 */
ystride = width * bpp + 1;
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi);
if (mipi->force_clk_lane_hs) {
u32 tmp;
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp |= (1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
}
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
if (mfd->op_enable)
ret = panel_next_on(pdev);
mipi_dsi_op_mode_config(mipi->mode);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (mdp_rev >= MDP_REV_41) {
if (gpio_request(vsync_gpio,
"MDP_VSYNC") == 0)
gpio_direction_input(
vsync_gpio);
else
pr_err("%s: unable to \
request gpio=%d\n",
__func__, vsync_gpio);
} else if (mdp_rev == MDP_REV_303) {
if (!tlmm_settings && gpio_request(
vsync_gpio, "MDP_VSYNC") == 0) {
ret = gpio_tlmm_config(
GPIO_CFG(
vsync_gpio, 1,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (ret) {
pr_err(
"%s: unable to config \
tlmm = %d\n",
__func__, vsync_gpio);
}
tlmm_settings = TRUE;
gpio_direction_input(
vsync_gpio);
} else {
if (!tlmm_settings) {
pr_err(
"%s: unable to request \
gpio=%d\n",
__func__, vsync_gpio);
}
}
}
static int mipi_dsi_off(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
struct msm_panel_info *pinfo;
pr_debug("%s+:\n", __func__);
mfd = platform_get_drvdata(pdev);
pinfo = &mfd->panel_info;
printk(KERN_INFO"%s is started.. \n", __func__);
if (mdp_rev >= MDP_REV_41 && mfd->panel_info.type == MIPI_CMD_PANEL)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
mipi_dsi_prepare_clocks();
mipi_dsi_ahb_ctrl(1);
mipi_dsi_clk_enable();
/* make sure dsi_cmd_mdp is idle */
mipi_dsi_cmd_mdp_busy();
}
/*
* Desctiption: change to DSI_CMD_MODE since it needed to
* tx DCS dsiplay off comamnd to panel
*/
#if defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_WXGA_PT) \
|| defined(CONFIG_FB_MSM_MIPI_HITACHI_VIDEO_HD_PT) \
|| defined(CONFIG_FB_MSM_MIPI_DSI_LGIT_FHD)
//for power sequence of lgit panel
#else
mipi_dsi_op_mode_config(DSI_CMD_MODE);
#endif
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (MDP_REV_303 != mdp_rev)
gpio_free(vsync_gpio);
}
mipi_dsi_set_tear_off(mfd);
}
}
#if defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_WXGA_PT) \
|| defined(CONFIG_FB_MSM_MIPI_HITACHI_VIDEO_HD_PT) \
|| defined(CONFIG_FB_MSM_MIPI_DSI_LGIT_FHD)
//for power sequence of lgit panel.
#else
ret = panel_next_off(pdev);
#endif
#ifdef CONFIG_MSM_BUS_SCALING
mdp_bus_scale_update_request(0);
#endif
mipi_dsi_clk_disable();
/* disbale dsi engine */
MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0);
mipi_dsi_phy_ctrl(0);
mipi_dsi_ahb_ctrl(0);
mipi_dsi_unprepare_clocks();
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(0);
if (mdp_rev >= MDP_REV_41 && mfd->panel_info.type == MIPI_CMD_PANEL)
mutex_unlock(&mfd->dma->ov_mutex);
else
up(&mfd->dma->mutex);
pr_debug("End of %s ....:\n", __func__);
printk(KERN_INFO"%s is ended.. \n", __func__);
return ret;
}
static int mipi_dsi_off(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
struct msm_panel_info *pinfo;
pr_debug("%s+:\n", __func__);
mfd = platform_get_drvdata(pdev);
pinfo = &mfd->panel_info;
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
mipi_dsi_prepare_clocks();
mipi_dsi_ahb_ctrl(1);
mipi_dsi_clk_enable();
mipi_dsi_cmd_mdp_busy();
}
mipi_dsi_op_mode_config(DSI_CMD_MODE);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (MDP_REV_303 != mdp_rev)
gpio_free(vsync_gpio);
}
if (!mfd->panel_info.lcdc.no_set_tear)
mipi_dsi_set_tear_off(mfd);
}
}
ret = panel_next_off(pdev);
spin_lock_bh(&dsi_clk_lock);
mipi_dsi_clk_disable();
MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0);
mipi_dsi_phy_ctrl(0);
mipi_dsi_ahb_ctrl(0);
spin_unlock_bh(&dsi_clk_lock);
mipi_dsi_unprepare_clocks();
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(0);
if (mdp_rev >= MDP_REV_41)
mutex_unlock(&mfd->dma->ov_mutex);
else
up(&mfd->dma->mutex);
pr_debug("%s-:\n", __func__);
return ret;
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
int target_type = 0;
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
local_bh_disable();
mipi_dsi_clk_enable();
local_bh_enable();
#ifndef CONFIG_FB_MSM_MDP303
mdp4_overlay_dsi_state_set(ST_DSI_RESUME);
#endif
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi_dsi_phy_ctrl(1);
if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
mipi = &mfd->panel_info.mipi;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.mipi.xres_pad;
dummy_yres = mfd->panel_info.mipi.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
/* DSI_LAN_SWAP_CTRL */
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3; /* Default format set to RGB888 */
ystride = width * bpp + 1;
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi);
mipi_dsi_cmd_bta_sw_trigger(); /* clean up ack_err_status */
ret = panel_next_on(pdev);
mipi_dsi_op_mode_config(mipi->mode);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio > 0) {
if (gpio_request(vsync_gpio, "MDP_VSYNC") == 0)
gpio_direction_input(vsync_gpio);
else
pr_err("%s: unable to request gpio=%d\n",
__func__, vsync_gpio);
}
mipi_dsi_set_tear_on(mfd);
}
}
#ifdef CONFIG_MSM_BUS_SCALING
mdp_bus_scale_update_request(2);
#endif
return ret;
}
static int mipi_dsi_off(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
struct msm_panel_info *pinfo;
uint32 dsi_ctrl;
pr_debug("%s+:\n", __func__);
mfd = platform_get_drvdata(pdev);
pinfo = &mfd->panel_info;
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
mipi_dsi_prepare_clocks();
mipi_dsi_ahb_ctrl(1);
mipi_dsi_clk_enable();
/* make sure dsi_cmd_mdp is idle */
mipi_dsi_cmd_mdp_busy();
}
/*
* Desctiption: change to DSI_CMD_MODE since it needed to
* tx DCS dsiplay off comamnd to panel
* mipi_dsi_op_mode_config(DSI_CMD_MODE);
*/
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (MDP_REV_303 != mdp_rev)
gpio_free(vsync_gpio);
}
mipi_dsi_set_tear_off(mfd);
}
}
ret = panel_next_off(pdev);
spin_lock_bh(&dsi_clk_lock);
mipi_dsi_clk_disable();
/* disbale dsi engine */
dsi_ctrl = MIPI_INP(MIPI_DSI_BASE + 0x0000);
dsi_ctrl &= ~0x01;
MIPI_OUTP(MIPI_DSI_BASE + 0x0000, dsi_ctrl);
MIPI_OUTP(MIPI_DSI_BASE + 0x010c, 0); /* DSI_INTL_CTRL */
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
mipi_dsi_phy_ctrl(0);
mipi_dsi_ahb_ctrl(0);
spin_unlock_bh(&dsi_clk_lock);
mipi_dsi_unprepare_clocks();
usleep(5000);
if (mipi_dsi_pdata && mipi_dsi_pdata->active_reset)
mipi_dsi_pdata->active_reset(0); /* low */
usleep(2000); /*1ms delay(minimum) required between reset low and AVDD off*/
if (mipi_dsi_pdata && mipi_dsi_pdata->panel_power_save)
mipi_dsi_pdata->panel_power_save(0);
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(0);
if (mdp_rev >= MDP_REV_41)
mutex_unlock(&mfd->dma->ov_mutex);
else
up(&mfd->dma->mutex);
pr_debug("%s-:\n", __func__);
return ret;
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
int target_type = 0;
u32 tmp;
#if defined(CONFIG_FB_MSM_MIPI_RENESAS_TFT_VIDEO_FULL_HD_PT_PANEL)
static int is_booting = 1;
#endif
#ifdef CONFIG_FB_MSM_LCD_NOTIFY
lcd_notifier_call_chain(LCD_EVENT_ON_START, NULL);
#endif
pr_debug("%s+:\n", __func__);
#if defined(CONFIG_MIPI_SAMSUNG_ESD_REFRESH) || defined(CONFIG_ESD_ERR_FG_RECOVERY)
pdev_for_esd = pdev;
#endif
#if defined (CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_QHD_PT)
if (get_lcd_attached() == 0)
return ENODEV;
#endif
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
esc_byte_ratio = pinfo->mipi.esc_byte_ratio;
if (mipi_dsi_pdata && mipi_dsi_pdata->power_common)
mipi_dsi_pdata->power_common();
#if defined(CONFIG_SUPPORT_SECOND_POWER)
#if defined(CONFIG_FB_MSM_MIPI_RENESAS_TFT_VIDEO_FULL_HD_PT_PANEL)
if( is_booting == 1 )
{
is_booting = 0;
#if defined(CONFIG_MACH_JACTIVE_ATT) || defined(CONFIG_MACH_JACTIVE_EUR)
usleep(5000);
if (mipi_dsi_pdata && mipi_dsi_pdata->active_reset)
mipi_dsi_pdata->active_reset(0); /* low */
usleep(2000);
if (mipi_dsi_pdata && mipi_dsi_pdata->panel_power_save)
mipi_dsi_pdata->panel_power_save(0);
msleep(10);
#endif
}
#endif
if (mipi_dsi_pdata && mipi_dsi_pdata->panel_power_save)
mipi_dsi_pdata->panel_power_save(1);
#endif
#if !defined(CONFIG_SEC_PRODUCT_8930) && !defined(CONFIG_SEC_PRODUCT_8960)
if (system_rev == 6)
mdelay(500);
#endif
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
cont_splash_clk_ctrl(0);
mipi_dsi_prepare_clocks();
mipi_dsi_ahb_ctrl(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
mipi_dsi_phy_ctrl(1);
if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
mipi_dsi_clk_enable();
#if defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_QHD_PT_PANEL)
mipi_dsi_configure_dividers(60);
#endif
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi = &mfd->panel_info.mipi;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.lcdc.xres_pad;
dummy_yres = mfd->panel_info.lcdc.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
/* DSI_LAN_SWAP_CTRL */
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3; /* Default format set to RGB888 */
ystride = width * bpp + 1;
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi);
#if defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_HD_PT_PANEL)
{
u32 tmp_reg0c, tmp_rega8;
udelay(200);
/* backup register values */
tmp_reg0c = MIPI_INP(MIPI_DSI_BASE + 0x000c);
tmp_rega8 = MIPI_INP(MIPI_DSI_BASE + 0xA8);
/* Clear HS mode assertion and related flags */
MIPI_OUTP(MIPI_DSI_BASE + 0x0c, 0x8000);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, 0x0);
wmb();
mdelay(10);
if (mipi_dsi_pdata && mipi_dsi_pdata->lcd_rst_up)
mipi_dsi_pdata->lcd_rst_up();
/* restore previous values */
MIPI_OUTP(MIPI_DSI_BASE + 0x0c, tmp_reg0c);
MIPI_OUTP(MIPI_DSI_BASE + 0xa8, tmp_rega8);
wmb();
}
#else
msleep(10);
#if defined (CONFIG_MIPI_DSI_RESET_LP11)
/* LP11 */
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp &= ~(1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
/* LP11 */
usleep(5000);
if (mipi_dsi_pdata && mipi_dsi_pdata->active_reset)
mipi_dsi_pdata->active_reset(1); /* high */
usleep(10000);
#endif
#if defined(CONFIG_MACH_LT02_SPR) || defined(CONFIG_MACH_LT02_ATT) || defined(CONFIG_MACH_LT02_TMO)
if(system_rev)
ret = panel_next_on(pdev);
#elif defined(CONFIG_MACH_LT02_CHN_CTC)
ret = panel_next_on(pdev);
#endif
#endif
/* always high */
if (mipi->force_clk_lane_hs) {
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp |= (1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
}
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
#if !defined(CONFIG_MACH_LT02_CHN_CTC)
#if defined(CONFIG_MACH_LT02_SPR) || defined(CONFIG_MACH_LT02_ATT) || defined(CONFIG_MACH_LT02_TMO)
if(!system_rev)
ret = panel_next_on(pdev);
#else
ret = panel_next_on(pdev);
#endif
#endif
mipi_dsi_op_mode_config(mipi->mode);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (mdp_rev >= MDP_REV_41) {
if (gpio_request(vsync_gpio,
"MDP_VSYNC") == 0)
gpio_direction_input(
vsync_gpio);
else
pr_err("%s: unable to \
request gpio=%d\n",
__func__, vsync_gpio);
} else if (mdp_rev == MDP_REV_303) {
if (!tlmm_settings && gpio_request(
vsync_gpio, "MDP_VSYNC") == 0) {
ret = gpio_tlmm_config(
GPIO_CFG(
vsync_gpio, 1,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (ret) {
pr_err(
"%s: unable to config \
tlmm = %d\n",
__func__, vsync_gpio);
}
tlmm_settings = TRUE;
gpio_direction_input(
vsync_gpio);
} else {
if (!tlmm_settings) {
pr_err(
"%s: unable to request \
gpio=%d\n",
__func__, vsync_gpio);
}
}
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
int target_type = 0;
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
local_bh_disable();
mipi_dsi_clk_enable();
local_bh_enable();
#ifndef CONFIG_FB_MSM_MDP303
mdp4_overlay_dsi_state_set(ST_DSI_RESUME);
#endif
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
mfd->dma->busy = FALSE;//add by Wenke Ma, as zygote died and restart then the isr cannot enter and this flag doesnot set false
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi_dsi_phy_ctrl(1);
if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
mipi = &mfd->panel_info.mipi;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.mipi.xres_pad;
dummy_yres = mfd->panel_info.mipi.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
/* DSI_LAN_SWAP_CTRL */
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3; /* Default format set to RGB888 */
ystride = width * bpp + 1;
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi);
ret = panel_next_on(pdev);
mipi_dsi_op_mode_config(mipi->mode);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio > 0) {
if (mdp_rev >= MDP_REV_41) {
if (gpio_request(vsync_gpio,
"MDP_VSYNC") == 0)
gpio_direction_input(
vsync_gpio);
else
pr_err("%s: unable to \
request gpio=%d\n",
__func__, vsync_gpio);
} else if (mdp_rev == MDP_REV_303) {
if (!tlmm_settings && gpio_request(
vsync_gpio, "MDP_VSYNC") == 0) {
ret = gpio_tlmm_config(
GPIO_CFG(
vsync_gpio, 1,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (ret) {
pr_err(
"%s: unable to config \
tlmm = %d\n",
__func__, vsync_gpio);
}
tlmm_settings = TRUE;
gpio_direction_input(
vsync_gpio);
} else {
if (!tlmm_settings) {
pr_err(
"%s: unable to request \
gpio=%d\n",
__func__, vsync_gpio);
}
}
}
static int mipi_dsi_off(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
struct msm_panel_info *pinfo;
mfd = platform_get_drvdata(pdev);
pinfo = &mfd->panel_info;
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
htc_mdp_sem_down(current, &mfd->dma->mutex);
mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND);
mipi_dsi_clk_cfg(1);
mipi_dsi_cmd_mdp_busy();
mipi_dsi_op_mode_config(DSI_CMD_MODE);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (MDP_REV_303 != mdp_rev)
gpio_free(vsync_gpio);
}
mipi_dsi_set_tear_off(mfd);
}
}
if (panel_type != PANEL_ID_PROTOU_LG && panel_type != PANEL_ID_PROTODCG_LG)
ret = panel_next_off(pdev);
#ifdef CONFIG_MSM_BUS_SCALING
mdp_bus_scale_update_request(0);
#endif
spin_lock_bh(&dsi_clk_lock);
mipi_dsi_clk_disable();
MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0);
mipi_dsi_phy_ctrl(0);
mipi_dsi_ahb_ctrl(0);
spin_unlock_bh(&dsi_clk_lock);
mipi_dsi_unprepare_clocks();
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(0);
if (mdp_rev >= MDP_REV_41)
mutex_unlock(&mfd->dma->ov_mutex);
else
htc_mdp_sem_up(&mfd->dma->mutex);
pr_debug("%s-:\n", __func__);
return ret;
}
/*LGE_CHANGE_E LCD Reset After Data Pulled Down*/
static int mipi_dsi_off(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
struct msm_panel_info *pinfo;
mfd = platform_get_drvdata(pdev);
pinfo = &mfd->panel_info;
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND);
/*
* Description: dsi clock is need to perform shutdown.
* mdp4_dsi_cmd_dma_busy_wait() will enable dsi clock if disabled.
* also, wait until dma (overlay and dmap) finish.
*/
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (mdp_rev >= MDP_REV_41) {
mdp4_dsi_cmd_dma_busy_wait(mfd);
mdp4_dsi_blt_dmap_busy_wait(mfd);
mipi_dsi_mdp_busy_wait(mfd);
} else {
mdp3_dsi_cmd_dma_busy_wait(mfd);
}
}
/*
* Desctiption: change to DSI_CMD_MODE since it needed to
* tx DCS dsiplay off comamnd to panel
*/
//LGE_CHANGE_S [Kiran] Change LCD sleep sequence
/*LCD Reset After data pulled Down*/
#if 0
if(lglogo_firstboot)
{
mipi_dsi_op_mode_config(DSI_CMD_MODE);
}
#endif
/*LGE_CHANGE_E LCD Reset After Data Pulled Down*/
//LGE_CHANGE_E [Kiran] Change LCD sleep sequence
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (MDP_REV_303 != mdp_rev)
gpio_free(vsync_gpio);
}
mipi_dsi_set_tear_off(mfd);
}
}
ret = panel_next_off(pdev);
#ifdef CONFIG_MSM_BUS_SCALING
mdp_bus_scale_update_request(0);
#endif
/*In case of ESD no delays required in power off*/
//LGE_CHANGE_S [Kiran] Change LCD sleep sequence
#ifdef CONFIG_LGE_LCD_ESD_DETECTION
if (true == is_esd_occured)
{
printk("ESD.Paneloff ASAP\n");
}
else
#endif
msleep(300);
//LGE_CHANGE_E [Kiran] Change LCD sleep sequence
#ifdef CONFIG_FB_MSM_MIPI_DSI_LG4573B_BOOT_LOGO
if(lglogo_firstboot)
{
printk(KERN_INFO "[DISPLAY]::%s\n",__func__);
local_bh_disable();
lglogo_mipi_dsi_clk_disable();
local_bh_enable();
}
else
#endif
{
local_bh_disable();
mipi_dsi_clk_disable();
local_bh_enable();
}
/* disbale dsi engine */
MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0);
mipi_dsi_phy_ctrl(0);
#ifdef CONFIG_FB_MSM_MIPI_DSI_LG4573B_BOOT_LOGO
if(!lglogo_firstboot)
#endif
{
local_bh_disable();
mipi_dsi_ahb_ctrl(0);
local_bh_enable();
}
//LGE_CHANGE_S [Kiran] Change LCD sleep sequence
#if 1
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
/*Turning off DMA_P block*/
mdp_pipe_ctrl(MDP_DMA2_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
#endif
//LGE_CHANGE_E [Kiran] Change LCD sleep sequence
/*LCD Reset After data pulled Down*/
mipi_ldp_lcd_panel_poweroff();
/*LGE_CHANGE_E LCD Reset After Data Pulled Down*/
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(0);
if (mdp_rev >= MDP_REV_41)
mutex_unlock(&mfd->dma->ov_mutex);
else
up(&mfd->dma->mutex);
pr_debug("%s-:\n", __func__);
#ifdef CONFIG_FB_MSM_MIPI_DSI_LG4573B_BOOT_LOGO
lglogo_firstboot = FALSE;
#endif
return ret;
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
int target_type = 0;
int old_nice;
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
/*
* Now first priority is to turn on LCD quickly for better
* user experience. We set current task to higher priority
* and restore it after panel is on.
*/
old_nice = task_nice(current);
if (old_nice > -20)
set_user_nice(current, -20);
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
cont_splash_clk_ctrl();
mipi_dsi_ahb_ctrl(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
mipi = &mfd->panel_info.mipi;
/* Clean up the force clk lane to enter HS from previous boot */
if ((mfd->panel_info.type == MIPI_VIDEO_PANEL) &&
mipi->force_clk_lane_hs)
MIPI_OUTP(MIPI_DSI_BASE + 0x00a8, 0);
mipi_dsi_phy_ctrl(1);
if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
mipi_dsi_clk_enable();
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.mipi.xres_pad;
dummy_yres = mfd->panel_info.mipi.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
/* DSI_LAN_SWAP_CTRL */
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3; /* Default format set to RGB888 */
ystride = width * bpp + 1;
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi);
/*
* The MIPI host is done with INIT now, the lines are at LP-11,
* and it is safe to turn on the power to the panel and get it out
* of reset
*/
if (mipi_dsi_pdata && mipi_dsi_pdata->panel_power_save)
mipi_dsi_pdata->panel_power_save(1);
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
if ((mfd->panel_info.type == MIPI_VIDEO_PANEL) &&
mipi->force_clk_lane_hs) {
u32 tmp;
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp |= (1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
}
ret = panel_next_on(pdev);
mipi_dsi_op_mode_config(mipi->mode);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (mdp_rev >= MDP_REV_41) {
if (gpio_request(vsync_gpio,
"MDP_VSYNC") == 0)
gpio_direction_input(
vsync_gpio);
else
pr_err("%s: unable to \
request gpio=%d\n",
__func__, vsync_gpio);
} else if (mdp_rev == MDP_REV_303) {
if (!tlmm_settings && gpio_request(
vsync_gpio, "MDP_VSYNC") == 0) {
ret = gpio_tlmm_config(
GPIO_CFG(
vsync_gpio, 1,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (ret) {
pr_err(
"%s: unable to config \
tlmm = %d\n",
__func__, vsync_gpio);
}
tlmm_settings = TRUE;
gpio_direction_input(
vsync_gpio);
} else {
if (!tlmm_settings) {
pr_err(
"%s: unable to request \
gpio=%d\n",
__func__, vsync_gpio);
}
}
}
static void mipi_dsi_shutdown(struct platform_device *pdev)
{
if(bmipi_off == 0) {
int ret = 0;
struct msm_fb_data_type *mfd;
struct msm_panel_info *pinfo;
pr_debug("Start of %s....:\n", __func__);
mfd = platform_get_drvdata(pdev);
pinfo = &mfd->panel_info;
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
mipi_dsi_prepare_clocks();
mipi_dsi_ahb_ctrl(1);
mipi_dsi_clk_enable();
/* make sure dsi_cmd_mdp is idle */
mipi_dsi_cmd_mdp_busy();
}
/*
* Desctiption: change to DSI_CMD_MODE since it needed to
* tx DCS dsiplay off comamnd to panel
*/
mipi_dsi_op_mode_config(DSI_CMD_MODE);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (MDP_REV_303 != mdp_rev)
gpio_free(vsync_gpio);
}
mipi_dsi_set_tear_off(mfd);
}
}
ret = panel_next_off(pdev);
#if defined(CONFIG_MDP_RUNTIME_BANDWIDTH)
#else
#ifdef CONFIG_MSM_BUS_SCALING
mdp_bus_scale_update_request(0);
#endif
#endif
mipi_dsi_clk_disable();
/* disbale dsi engine */
MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0);
mipi_dsi_phy_ctrl(0);
mipi_dsi_ahb_ctrl(0);
mipi_dsi_unprepare_clocks();
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(0);
if (mdp_rev >= MDP_REV_41)
mutex_unlock(&mfd->dma->ov_mutex);
else
up(&mfd->dma->mutex);
pr_debug("End of %s ....:\n", __func__);
bmipi_off = 1;
}
}
int mipi_dsi_off(struct platform_device *pdev)
#endif
/* OPPO 2013-02-04 zhengzk Modify end */
{
int ret = 0;
struct msm_fb_data_type *mfd;
struct msm_panel_info *pinfo;
pr_debug("%s+:\n", __func__);
mfd = platform_get_drvdata(pdev);
pinfo = &mfd->panel_info;
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
/*OPPO 2013-10-11 zhzhyon Add for reason*/
#ifdef PANEL_SRE
if(get_pcb_version() >= PCB_VERSION_EVT_N1)
{
mutex_lock(&sre_mutex);
}
#endif
/*OPPO 2013-10-11 zhzhyon Add end*/
mipi_dsi_prepare_ahb_clocks();
mipi_dsi_ahb_ctrl(1);
mipi_dsi_clk_enable();
/*OPPO 2013-10-11 zhzhyon Add for reason*/
#ifdef PANEL_SRE
if(get_pcb_version() >= PCB_VERSION_EVT_N1)
{
mutex_unlock(&sre_mutex);
}
#endif
/*OPPO 2013-10-11 zhzhyon Add end*/
/* make sure dsi_cmd_mdp is idle */
mipi_dsi_cmd_mdp_busy();
}
/*
* Desctiption: change to DSI_CMD_MODE since it needed to
* tx DCS dsiplay off comamnd to panel
*/
mipi_dsi_op_mode_config(DSI_CMD_MODE);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (MDP_REV_303 != mdp_rev)
gpio_free(vsync_gpio);
}
mipi_dsi_set_tear_off(mfd);
}
}
ret = panel_next_off(pdev);
spin_lock_bh(&dsi_clk_lock);
mipi_dsi_clk_disable();
/* disbale dsi engine */
MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0);
mipi_dsi_phy_ctrl(0);
mipi_dsi_ahb_ctrl(0);
spin_unlock_bh(&dsi_clk_lock);
mipi_dsi_unprepare_clocks();
mipi_dsi_unprepare_ahb_clocks();
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(0);
if (mdp_rev >= MDP_REV_41)
mutex_unlock(&mfd->dma->ov_mutex);
else
up(&mfd->dma->mutex);
pr_debug("%s-:\n", __func__);
return ret;
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
u32 tmp;
int target_type = 0;
int old_nice;
pr_debug("%s+:\n", __func__);
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
/*
* Now first priority is to turn on LCD quickly for better
* user experience. We set current task to higher priority
* and restore it after panel is on.
*/
old_nice = task_nice(current);
if (old_nice > -20)
set_user_nice(current, -20);
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
#if defined(CONFIG_FB_MSM_MIPI_PANEL_POWERON_LP11)
/*
* Fix for floating state of VDD line in toshiba chip
* */
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_client_power_save)
mipi_dsi_pdata->dsi_client_power_save(1);
#endif /* CONFIG_FB_MSM_MIPI_PANEL_POWERON_LP11 */
cont_splash_clk_ctrl(0);
mipi_dsi_prepare_ahb_clocks();
mipi_dsi_ahb_ctrl(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
mipi_dsi_phy_ctrl(1);
if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
mipi_dsi_clk_enable();
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi = &mfd->panel_info.mipi;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.lcdc.xres_pad;
dummy_yres = mfd->panel_info.lcdc.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
/* DSI_LAN_SWAP_CTRL */
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3; /* Default format set to RGB888 */
ystride = width * bpp + 1;
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi);
#if defined(CONFIG_FB_MSM_MIPI_PANEL_POWERON_LP11)
/*
* For TC358764 D2L IC, one of the requirement for power on
* is to maintain an LP11 state in data and clock lanes during
* power enabling and reset assertion. This change is to
* achieve that.
* */
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_client_power_save) {
u32 tmp_reg0c, tmp_rega8;
mipi_dsi_pdata->dsi_client_reset();
udelay(200);
/* backup register values */
tmp_reg0c = MIPI_INP(MIPI_DSI_BASE + 0x000c);
tmp_rega8 = MIPI_INP(MIPI_DSI_BASE + 0xA8);
/* Clear HS mode assertion and related flags */
MIPI_OUTP(MIPI_DSI_BASE + 0x0c, 0x8000);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, 0x0);
wmb();
mdelay(5);
/* restore previous values */
MIPI_OUTP(MIPI_DSI_BASE + 0x0c, tmp_reg0c);
MIPI_OUTP(MIPI_DSI_BASE + 0xa8, tmp_rega8);
wmb();
}
#endif /* CONFIG_FB_MSM_MIPI_PANEL_POWERON_LP11 */
#if defined(CONFIG_FB_MSM_MIPI_MAGNA_OLED_VIDEO_WVGA_PT)
/* LP11 */
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp &= ~(1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
/* LP11 */
usleep(5000);
if (mipi_dsi_pdata && mipi_dsi_pdata->active_reset)
mipi_dsi_pdata->active_reset(); /* high */
usleep(10000);
#endif
if (mipi->force_clk_lane_hs) {
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp |= (1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
}
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
ret = panel_next_on(pdev);
mipi_dsi_op_mode_config(mipi->mode);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (mdp_rev >= MDP_REV_41) {
if (gpio_request(vsync_gpio,
"MDP_VSYNC") == 0)
gpio_direction_input(
vsync_gpio);
else
pr_err("%s: unable to \
request gpio=%d\n",
__func__, vsync_gpio);
} else if (mdp_rev == MDP_REV_303) {
if (!tlmm_settings && gpio_request(
vsync_gpio, "MDP_VSYNC") == 0) {
ret = gpio_tlmm_config(
GPIO_CFG(
vsync_gpio, 1,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (ret) {
pr_err(
"%s: unable to config \
tlmm = %d\n",
__func__, vsync_gpio);
}
tlmm_settings = TRUE;
gpio_direction_input(
vsync_gpio);
} else {
if (!tlmm_settings) {
pr_err(
"%s: unable to request \
gpio=%d\n",
__func__, vsync_gpio);
}
}
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
int target_type = 0;
#if defined (CONFIG_MIPI_DSI_RESET_LP11)
u32 tmp;
#endif
pr_info("%s+:\n", __func__);
#if defined(CONFIG_MIPI_SAMSUNG_ESD_REFRESH) || defined(CONFIG_ESD_ERR_FG_RECOVERY)
pdev_for_esd = pdev;
#endif
#ifdef CONFIG_DUAL_LCD
if (mipi_dsi_pdev_switch == NULL)
pr_debug( "%s : pdev_switch updated", __func__ );
mipi_dsi_pdev_switch = pdev;
#endif // #ifdef CONFIG_DUAL_LCD
#if defined (CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_QHD_PT)
if (get_lcd_attached() == 0)
return ENODEV;
#endif
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
cont_splash_clk_ctrl(0);
#if defined(CONFIG_MACH_LT02_CHN_CTC)
if (mipi_dsi_pdata && mipi_dsi_pdata->active_reset)
mipi_dsi_pdata->active_reset(1); /* high */
usleep(4000);
ret = panel_next_on(pdev);
usleep(1000);
#endif
mipi_dsi_prepare_ahb_clocks();
mipi_dsi_ahb_ctrl(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
mipi_dsi_phy_ctrl(1);
if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
mipi_dsi_clk_enable();
#if defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_QHD_PT_PANEL)
mipi_dsi_configure_dividers(60);
#endif
#if defined(CONFIG_RUNTIME_MIPI_CLK_CHANGE) && defined(CONFIG_FB_MSM_MIPI_AMS367_OLED_VIDEO_WVGA_PT_PANEL)
if (is_S6E88A())
mipi_AMS367AV_dynamic_fps_folder(in_mipi_dsi_NULL, pinfo);
else
mipi_AMS367_dynamic_fps_folder(in_mipi_dsi_NULL, pinfo);
#endif
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi = &mfd->panel_info.mipi;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.lcdc.xres_pad;
dummy_yres = mfd->panel_info.lcdc.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
/* DSI_LAN_SWAP_CTRL */
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3; /* Default format set to RGB888 */
ystride = width * bpp + 1;
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi);
#if defined (CONFIG_MIPI_DSI_RESET_LP11)
/* LP11 */
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp &= ~(1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
/* LP11 */
#if !defined(CONFIG_MACH_LT02_CHN_CTC)
usleep(5000);
if (mipi_dsi_pdata && mipi_dsi_pdata->active_reset)
mipi_dsi_pdata->active_reset(1); /* high */
usleep(10000);
#endif
#endif
#if defined(CONFIG_MACH_LT02_SPR) || defined(CONFIG_MACH_LT02_ATT)
if(system_rev)
ret = panel_next_on(pdev);
#endif
if (mipi->force_clk_lane_hs) {
#ifndef CONFIG_MIPI_DSI_RESET_LP11
u32 tmp;
#endif
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp |= (1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
}
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
#if !defined(CONFIG_MACH_LT02_CHN_CTC)
#if defined(CONFIG_MACH_LT02_SPR) || defined(CONFIG_MACH_LT02_ATT)
if(!system_rev)
ret = panel_next_on(pdev);
#else
ret = panel_next_on(pdev);
#endif
#endif
mipi_dsi_op_mode_config(mipi->mode);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (mdp_rev >= MDP_REV_41) {
if (gpio_request(vsync_gpio,
"MDP_VSYNC") == 0)
gpio_direction_input(
vsync_gpio);
else
pr_err("%s: unable to \
request gpio=%d\n",
__func__, vsync_gpio);
} else if (mdp_rev == MDP_REV_303) {
if (!tlmm_settings && gpio_request(
vsync_gpio, "MDP_VSYNC") == 0) {
ret = gpio_tlmm_config(
GPIO_CFG(
vsync_gpio, 1,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (ret) {
pr_err(
"%s: unable to config \
tlmm = %d\n",
__func__, vsync_gpio);
}
tlmm_settings = TRUE;
gpio_direction_input(
vsync_gpio);
} else {
if (!tlmm_settings) {
pr_err(
"%s: unable to request \
gpio=%d\n",
__func__, vsync_gpio);
}
}
}
static int mipi_dsi_off(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
struct msm_panel_info *pinfo;
mfd = platform_get_drvdata(pdev);
pinfo = &mfd->panel_info;
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND);
/*
* Desctiption: change to DSI_CMD_MODE since it needed to
* tx DCS dsiplay off comamnd to panel
*/
mipi_dsi_op_mode_config(DSI_CMD_MODE);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (MDP_REV_303 != mdp_rev)
gpio_free(vsync_gpio);
}
mipi_dsi_set_tear_off(mfd);
}
}
ret = panel_next_off(pdev);
#ifdef CONFIG_MSM_BUS_SCALING
mdp_bus_scale_update_request(0);
#endif
spin_lock_bh(&dsi_clk_lock);
mipi_dsi_clk_disable();
/* disbale dsi engine */
MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0);
mipi_dsi_phy_ctrl(0);
mipi_dsi_ahb_ctrl(0);
spin_unlock_bh(&dsi_clk_lock);
mipi_dsi_unprepare_clocks();
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(0);
if (mdp_rev >= MDP_REV_41)
mutex_unlock(&mfd->dma->ov_mutex);
else
up(&mfd->dma->mutex);
pr_debug("%s-:\n", __func__);
return ret;
}
static int mipi_dsi_off(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
struct msm_panel_info *pinfo;
PR_DISP_DEBUG(" %s\n", __func__);
mfd = platform_get_drvdata(pdev);
pinfo = &mfd->panel_info;
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
htc_mdp_sem_down(current, &mfd->dma->mutex);
mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND);
/*
* Description: dsi clock is need to perform shutdown.
* mdp4_dsi_cmd_dma_busy_wait() will enable dsi clock if disabled.
* also, wait until dma (overlay and dmap) finish.
*/
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (mdp_rev >= MDP_REV_41) {
mdp4_dsi_cmd_dma_busy_wait(mfd);
mdp4_dsi_blt_dmap_busy_wait(mfd);
} else {
mdp3_dsi_cmd_dma_busy_wait(mfd);
}
}
/*
* Desctiption: change to DSI_CMD_MODE since it needed to
* tx DCS dsiplay off comamnd to panel
*/
mipi_dsi_op_mode_config(DSI_CMD_MODE);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio > 0) {
if (MDP_REV_303 != mdp_rev)
gpio_free(vsync_gpio);
}
mipi_dsi_set_tear_off(mfd);
}
}
ret = panel_next_off(pdev);
#ifdef CONFIG_MSM_BUS_SCALING
mdp_bus_scale_update_request(0);
#endif
/* disbale dsi engine */
MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0);
mipi_dsi_phy_ctrl(0);
local_bh_disable();
mipi_dsi_clk_disable();
local_bh_enable();
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(0);
if (mdp_rev >= MDP_REV_41)
mutex_unlock(&mfd->dma->ov_mutex);
else
htc_mdp_sem_up(&mfd->dma->mutex);
return ret;
}
static int mipi_dsi_off(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
struct msm_panel_info *pinfo;
pr_debug("%s+:\n", __func__);
mfd = platform_get_drvdata(pdev);
pinfo = &mfd->panel_info;
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
mipi_dsi_prepare_clocks();
mipi_dsi_ahb_ctrl(1);
mipi_dsi_clk_enable();
/* make sure dsi_cmd_mdp is idle */
mipi_dsi_cmd_mdp_busy();
}
/*
* Desctiption: change to DSI_CMD_MODE since it needed to
* tx DCS dsiplay off comamnd to panel
*/
mipi_dsi_op_mode_config(DSI_CMD_MODE);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (MDP_REV_303 != mdp_rev)
gpio_free(vsync_gpio);
}
mipi_dsi_set_tear_off(mfd);
}
}
ret = panel_next_off(pdev);
#if defined(CONFIG_FB_MSM_MIPI_S6E8AA0_HD720_PANEL) || \
defined(CONFIG_FB_MSM_MIPI_S6E8AA0_WXGA_Q1_PANEL)
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, 0x00000000); // for LCD-on when wakeup
#endif
spin_lock_bh(&dsi_clk_lock);
mipi_dsi_clk_disable();
/* disbale dsi engine */
MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0);
mipi_dsi_phy_ctrl(0);
mipi_dsi_ahb_ctrl(0);
spin_unlock_bh(&dsi_clk_lock);
mipi_dsi_unprepare_clocks();
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(0);
if (mdp_rev >= MDP_REV_41)
mutex_unlock(&mfd->dma->ov_mutex);
else
up(&mfd->dma->mutex);
pr_debug("%s-:\n", __func__);
return ret;
}
int mipi_dsi_off(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
struct msm_panel_info *pinfo;
mfd = platform_get_drvdata(pdev);
pinfo = &mfd->panel_info;
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND);
/*
* Description: dsi clock is need to perform shutdown.
* mdp4_dsi_cmd_dma_busy_wait() will enable dsi clock if disabled.
* also, wait until dma (overlay and dmap) finish.
*/
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (mdp_rev >= MDP_REV_41) {
mdp4_dsi_cmd_dma_busy_wait(mfd);
mdp4_dsi_blt_dmap_busy_wait(mfd);
mipi_dsi_mdp_busy_wait(mfd);
} else {
mdp3_dsi_cmd_dma_busy_wait(mfd);
}
} else {
/* video mode, wait until fifo cleaned */
mipi_dsi_controller_cfg(0);
}
/*
* Desctiption: change to DSI_CMD_MODE since it needed to
* tx DCS dsiplay off comamnd to panel
*/
mipi_dsi_op_mode_config(DSI_CMD_MODE);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (MDP_REV_303 != mdp_rev)
gpio_free(vsync_gpio);
}
mipi_dsi_set_tear_off(mfd);
}
}
ret = panel_next_off(pdev);
#ifdef CONFIG_MSM_BUS_SCALING
mdp_bus_scale_update_request(0);
#endif
#if defined(CONFIG_FB_MSM_MIPI_S6E8AA0_HD720_PANEL) || \
defined(CONFIG_FB_MSM_MIPI_S6E8AA0_WXGA_Q1_PANEL)
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, 0x00000000); // for LCD-on when wakeup
#endif
local_bh_disable();
mipi_dsi_clk_disable();
local_bh_enable();
/* disbale dsi engine */
MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0);
mipi_dsi_phy_ctrl(0);
local_bh_disable();
mipi_dsi_ahb_ctrl(0);
local_bh_enable();
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(0);
if (mdp_rev >= MDP_REV_41)
mutex_unlock(&mfd->dma->ov_mutex);
else
up(&mfd->dma->mutex);
pr_debug("%s-:\n", __func__);
return ret;
}
static int mipi_dsi_off(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
struct msm_panel_info *pinfo;
#ifdef CONFIG_HUAWEI_KERNEL
struct mipi_panel_info *mipi;
unsigned int datamask = 0;
#endif
mfd = platform_get_drvdata(pdev);
pinfo = &mfd->panel_info;
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND);
/*
* Description: dsi clock is need to perform shutdown.
* mdp4_dsi_cmd_dma_busy_wait() will enable dsi clock if disabled.
* also, wait until dma (overlay and dmap) finish.
*/
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (mdp_rev >= MDP_REV_41) {
mdp4_dsi_cmd_dma_busy_wait(mfd);
mdp4_dsi_blt_dmap_busy_wait(mfd);
mipi_dsi_mdp_busy_wait(mfd);
} else {
mdp3_dsi_cmd_dma_busy_wait(mfd);
}
}
/*
* Desctiption: change to DSI_CMD_MODE since it needed to
* tx DCS dsiplay off comamnd to panel
*/
mipi_dsi_op_mode_config(DSI_CMD_MODE);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (MDP_REV_303 != mdp_rev)
gpio_free(vsync_gpio);
}
mipi_dsi_set_tear_off(mfd);
}
}
ret = panel_next_off(pdev);
#ifdef CONFIG_HUAWEI_KERNEL
mipi = &mfd->panel_info.mipi;
if (mipi->data_lane3)
datamask |= 1<<3;
if (mipi->data_lane2)
datamask |= 1<<2;
if (mipi->data_lane1)
datamask |= 1<<1;
if (mipi->data_lane0)
datamask |= 1<<0;
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, datamask );
mdelay(1);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, datamask|(1<<4));
mdelay(1);
#endif
#ifdef CONFIG_MSM_BUS_SCALING
mdp_bus_scale_update_request(0);
#endif
local_bh_disable();
mipi_dsi_clk_disable();
local_bh_enable();
/* disbale dsi engine */
MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0);
mipi_dsi_phy_ctrl(0);
local_bh_disable();
mipi_dsi_ahb_ctrl(0);
local_bh_enable();
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(0);
if (mdp_rev >= MDP_REV_41)
mutex_unlock(&mfd->dma->ov_mutex);
else
up(&mfd->dma->mutex);
pr_debug("%s-:\n", __func__);
return ret;
}
static int mipi_dsi_off(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
struct msm_panel_info *pinfo;
pr_debug("%s+:\n", __func__);
mfd = platform_get_drvdata(pdev);
pinfo = &mfd->panel_info;
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
#if defined(FEATURE_SKYDISP_DISPLAY_FLICKER_SHARP_IPS)
//printk(KERN_ERR "[SKY_LCD] %s : %d\n", __FUNCTION__, __LINE__);
ret = panel_next_off(pdev);
#endif
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
mipi_dsi_prepare_clocks();
mipi_dsi_ahb_ctrl(1);
mipi_dsi_clk_enable();
/* make sure dsi_cmd_mdp is idle */
mipi_dsi_cmd_mdp_busy();
}
/*
* Desctiption: change to DSI_CMD_MODE since it needed to
* tx DCS dsiplay off comamnd to panel
*/
mipi_dsi_op_mode_config(DSI_CMD_MODE);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (MDP_REV_303 != mdp_rev)
gpio_free(vsync_gpio);
}
mipi_dsi_set_tear_off(mfd);
}
}
#if defined(FEATURE_SKYDISP_DISPLAY_FLICKER_SHARP_IPS)
/* panel_next_off changed : set before mipi_clock/mode_config etc... */
#else
ret = panel_next_off(pdev);
#endif
#ifdef CONFIG_MSM_BUS_SCALING
mdp_bus_scale_update_request(0);
#endif
mipi_dsi_clk_disable();
/* disbale dsi engine */
MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0);
mipi_dsi_phy_ctrl(0);
mipi_dsi_ahb_ctrl(0);
mipi_dsi_unprepare_clocks();
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(0);
if (mdp_rev >= MDP_REV_41)
mutex_unlock(&mfd->dma->ov_mutex);
else
up(&mfd->dma->mutex);
pr_debug("End of %s ....:\n", __func__);
return ret;
}