__init void mips_set_machine_name(const char *name)
{
if (name == NULL)
return;
strlcpy(mips_machine_name, name, sizeof(mips_machine_name));
pr_info("MIPS: machine is %s\n", mips_get_machine_name());
}
/*
* Init the hEX (PoE) lite hardware (QCA953x).
* The 750UP r2 (hEX PoE lite) is nearly identical to the hAP, only without
* WLAN. The 750 r2 (hEX lite) is nearly identical to the 750UP r2, only
* without USB and POE. The 750P Pbr2 (Powerbox) is nearly identical to hEX PoE
* lite, only without USB. It shares the same bootloader board identifier.
*/
static void __init rb750upr2_setup(void)
{
u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_SSR;
if (!rbspi_platform_setup())
return;
/* differentiate the hEX lite from the hEX PoE lite */
if (strstr(mips_get_machine_name(), "750UP r2"))
flags |= RBSPI_HAS_USB | RBSPI_HAS_POE;
/* differentiate the Powerbox from the hEX lite */
else if (strstr(mips_get_machine_name(), "750P r2"))
flags |= RBSPI_HAS_POE;
rbspi_952_750r2_setup(flags);
}
/*
* Init the hAP (ac lite) hardware (QCA953x).
* The 951Ui-2nD (hAP) has 5 ethernet ports, with ports 2-5 being assigned
* to LAN on the casing, and port 1 being assigned to "internet" (WAN).
* Port 1 is connected to PHY4 (the ports are labelled in reverse physical
* number), so the SoC can be set to connect GMAC0 to PHY4 and GMAC1 to the
* internal switch for the LAN ports.
* The device also has USB, PoE output and an SSR used for LED multiplexing.
* The 952Ui-5ac2nD (hAP ac lite) is nearly identical to the hAP, it adds a
* QCA9887 5GHz radio via PCI and moves 2.4GHz from WLAN0 to WLAN1.
*/
static void __init rb952_setup(void)
{
u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_USB |
RBSPI_HAS_SSR | RBSPI_HAS_POE;
if (!rbspi_platform_setup())
return;
/* differentiate the hAP from the hAP ac lite */
if (strstr(mips_get_machine_name(), "952Ui-5ac2nD"))
flags |= RBSPI_HAS_WLAN1 | RBSPI_HAS_PCI;
else
flags |= RBSPI_HAS_WLAN0;
rbspi_952_750r2_setup(flags);
}
static int show_cpuinfo(struct seq_file *m, void *v)
{
struct proc_cpuinfo_notifier_args proc_cpuinfo_notifier_args;
unsigned long n = (unsigned long) v - 1;
unsigned int version = cpu_data[n].processor_id;
unsigned int fp_vers = cpu_data[n].fpu_id;
char fmt [64];
int i;
#ifdef CONFIG_SMP
if (!cpu_online(n))
return 0;
#endif
/*
* For the first processor also print the system type
*/
if (n == 0) {
seq_printf(m, "system type\t\t: %s\n", get_system_type());
if (mips_get_machine_name())
seq_printf(m, "machine\t\t\t: %s\n",
mips_get_machine_name());
}
seq_printf(m, "processor\t\t: %ld\n", n);
sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : "");
seq_printf(m, fmt, __cpu_name[n],
(version >> 4) & 0x0f, version & 0x0f,
(fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
cpu_data[n].udelay_val / (500000/HZ),
(cpu_data[n].udelay_val / (5000/HZ)) % 100);
seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
seq_printf(m, "microsecond timers\t: %s\n",
cpu_has_counter ? "yes" : "no");
seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
seq_printf(m, "extra interrupt vector\t: %s\n",
cpu_has_divec ? "yes" : "no");
seq_printf(m, "hardware watchpoint\t: %s",
cpu_has_watch ? "yes, " : "no\n");
if (cpu_has_watch) {
seq_printf(m, "count: %d, address/irw mask: [",
cpu_data[n].watch_reg_count);
for (i = 0; i < cpu_data[n].watch_reg_count; i++)
seq_printf(m, "%s0x%04x", i ? ", " : "" ,
cpu_data[n].watch_reg_masks[i]);
seq_printf(m, "]\n");
}
seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n",
cpu_has_mips16 ? " mips16" : "",
cpu_has_mdmx ? " mdmx" : "",
cpu_has_mips3d ? " mips3d" : "",
cpu_has_smartmips ? " smartmips" : "",
cpu_has_dsp ? " dsp" : "",
cpu_has_mipsmt ? " mt" : ""
);
seq_printf(m, "shadow register sets\t: %d\n",
cpu_data[n].srsets);
seq_printf(m, "kscratch registers\t: %d\n",
hweight8(cpu_data[n].kscratch_mask));
seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
#if defined(CONFIG_MIPS_MT_SMP)
if (cpu_has_mipsmt)
seq_printf(m, "VPE\t\t\t: %d\n", cpu_data[n].vpe_id);
#endif
sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
cpu_has_vce ? "%u" : "not available");
seq_printf(m, fmt, 'D', vced_count);
seq_printf(m, fmt, 'I', vcei_count);
proc_cpuinfo_notifier_args.m = m;
proc_cpuinfo_notifier_args.n = n;
raw_notifier_call_chain(&proc_cpuinfo_chain, 0,
&proc_cpuinfo_notifier_args);
seq_printf(m, "\n");
return 0;
}
static int show_cpuinfo(struct seq_file *m, void *v)
{
unsigned long n = (unsigned long) v - 1;
unsigned int version = cpu_data[n].processor_id;
unsigned int fp_vers = cpu_data[n].fpu_id;
char fmt [64];
int i;
struct thread_struct *mc_thread = ¤t->thread;
#ifdef CONFIG_SMP
if (!cpu_isset(n, cpu_online_map))
return 0;
#endif
/* For Magiccode */
/* For Magiccode, when current process uses emulated ARM native code: */
if (mc_thread->mcflags != CPU_MIPS) {
/* mimic cpuinfo of 2012 Nexus7 with NVidia Tegra3 T30L cpu */
seq_printf(m, "Processor\t: ARMv7 Processor rev 9 (v7l)\n");
seq_printf(m, "processor\t: 0\n");
seq_printf(m, "BogoMIPS\t: 1001.88\n\n");
/* show just one processor core */
seq_printf(m, "Features\t: swp half thumb fastmult vfp ");
if (mc_thread->mcflags == CPU_ARM_NEON)
seq_printf(m, "edsp neon ");
seq_printf(m, "vfpv3\n");
/* no thumbee or tls feature */
seq_printf(m, "CPU implementer\t: 0x41\n"); /* ARM */
seq_printf(m, "CPU architecture: 7\n");
seq_printf(m, "CPU variant\t: 0x2\n");
seq_printf(m, "CPU part\t: 0xc09\n"); /* Cortex-A9 */
seq_printf(m, "CPU revision\t: 9\n");
seq_printf(m, "\n");
return 0;
}
else {
/*
* For the first processor also print the system type
*/
unsigned int detected = 0;
rcu_read_lock();
if ((strcmp(current->parent->comm, "tv.apad:vplayer") == 0) ||
(strcmp(current->comm, "tv.apad:vplayer") == 0)) {
detected = 1;
}
rcu_read_unlock();
if (n == 0) {
seq_printf(m, "system type\t\t: %s\n", get_system_type());
if (mips_get_machine_name())
seq_printf(m, "machine\t\t\t: %s\n",
mips_get_machine_name());
}
if (detected == 0) {
seq_printf(m, "processor\t\t: %ld\n", n);
} else {
seq_printf(m, "processor\t\t: ARMv7 swp half thumb fastmult vfp edsp neon vfpv3 %ld\n ", n);
}
sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : "");
seq_printf(m, fmt, __cpu_name[n],
(version >> 4) & 0x0f, version & 0x0f,
(fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
cpu_data[n].udelay_val / (500000/HZ),
(cpu_data[n].udelay_val / (5000/HZ)) % 100);
seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
if (detected == 0) {
seq_printf(m, "microsecond timers\t: %s\n",
cpu_has_counter ? "yes" : "no");
}
seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
seq_printf(m, "extra interrupt vector\t: %s\n",
cpu_has_divec ? "yes" : "no");
seq_printf(m, "hardware watchpoint\t: %s",
cpu_has_watch ? "yes, " : "no\n");
if (cpu_has_watch) {
seq_printf(m, "count: %d, address/irw mask: [",
cpu_data[n].watch_reg_count);
for (i = 0; i < cpu_data[n].watch_reg_count; i++)
seq_printf(m, "%s0x%04x", i ? ", " : "" ,
cpu_data[n].watch_reg_masks[i]);
seq_printf(m, "]\n");
}
seq_printf(m, "microMIPS\t\t: %s\n", cpu_has_mmips ? "yes" : "no");
seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s%s\n",
cpu_has_mips16 ? " mips16" : "",
cpu_has_mdmx ? " mdmx" : "",
cpu_has_mips3d ? " mips3d" : "",
cpu_has_smartmips ? " smartmips" : "",
cpu_has_dsp ? " dsp" : "",
cpu_has_mipsmt ? " mt" : "",
cpu_has_mxu ? " mxu" : ""
);
seq_printf(m, "shadow register sets\t: %d\n",
cpu_data[n].srsets);
seq_printf(m, "kscratch registers\t: %d\n",
hweight8(cpu_data[n].kscratch_mask));
seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
cpu_has_vce ? "%u" : "not available");
seq_printf(m, fmt, 'D', vced_count);
seq_printf(m, fmt, 'I', vcei_count);
/* Android requires 'Hardware' to setup the init.%hardware%.rc */
seq_printf(m, "Hardware\t\t: %s\n", get_board_type());
seq_printf(m, "\n");
}
return 0;
}
