int mailbox_read(unsigned int channel) {
unsigned int mail;
printk("MAILBOX_READ: reading channel %x\n",
channel);
/* Channel must be 4-bits */
if (channel>15) {
printk("mailbox_read: channel too high\n",
channel);
return -1;
}
/* Wait until mailbox has something there */
while((mmio_read(MAILBOX_STATUS) & MAIL_EMPTY) ) {
printk("mailbox_read: mail_empty\n");
}
mail=mmio_read(MAILBOX_READ);
/* Got mail from the wrong channel!*/
/* FIXME: Should we try again? */
if ((mail&0xf)!=channel) {
printk("mailbox_read: read from wrong channel %x %x\n",
mail&0xf,channel);
return -1;
}
/* Return top 28 bits */
return mail&0xfffffff0;
}
static
int uart_proc_data()
{
if (mmio_read(UART0_FR) & (1 << 4))
return -1;
return mmio_read(UART0_DR);
}
void usDelay (unsigned nMicroSeconds)
{
unsigned int cur_timer = mmio_read(ARM_SYSTIMER_CLO);
unsigned int trigger_value = cur_timer + nMicroSeconds;
unsigned int rollover;
if (nMicroSeconds > 0)
{
if (trigger_value > cur_timer)
rollover = 0;
else
rollover = 1;
for (;;) {
cur_timer = mmio_read(ARM_SYSTIMER_CLO);
if (cur_timer < trigger_value) {
if (rollover) {
rollover = 0;
}
}
else if (!rollover) {
break;
}
}
}
}
void rtc_init(int minor)
{
uint32_t a = 0x0;
rtc_clk_init();
/*
* Steps to enable RTC
* 1. Enable the module clock domains (rtc_clk_init).
* 2. Enable the RTC module using CTRL_REG.RTC_disable. (Default enabled. Nothing done)
* 3. Enable the 32K clock from PER PLL, if using the internal RTC oscillator.
* 4. Write to the kick registers (KICK0R, KICK1R) in the RTC.
* 5. Configure the timer in RTCSS for desired application (set time and date, alarm wakeup, and so on).
* 6. Start the RTC (in CTRL_REG.STOP_RTC).
*/
rtc_write_enable();
a = setbit(a,0);
mmio_write(AM335X_RTC_BASE+AM335X_RTC_SYSCONFIG,a);
a = mmio_read(AM335X_RTC_BASE+AM335X_RTC_OSC_CLOCK);
a = setbit(a,6);
mmio_write(AM335X_RTC_BASE+AM335X_RTC_OSC_CLOCK,a);
a = mmio_read(AM335X_RTC_BASE+AM335X_RTC_CTRL_REG);
a = setbit(a,0);
mmio_write(AM335X_RTC_BASE+AM335X_RTC_CTRL_REG,a);
rtc_write_disable();
}
int uart_getc_timeout(useconds_t timeout)
{
TIMEOUT_WAIT((mmio_read(UART0_FR) & (1 << 4)) == 0, timeout);
if((mmio_read(UART0_FR) & (1 << 4)) == 0)
return mmio_read(UART0_DR) & 0xff;
else
return -1;
}
unsigned char uart_getc()
{
while(1)
{
if(mmio_read(AUX_MU_LSR_REG)&0x1) break;
}
return mmio_read(AUX_MU_IO_REG);
}
int mmrd (uint32_t addr, uint32_t u1)
{
extr(addr, addr, 2, 25);
addr = addr << 2;
mmio_write(FUC_MMIO_CTRL, addr | (u1 & 1) | 0x80000000);
while (mmio_read(FUC_MMIO_CTRL) & 0x80000000);
while (!(mmio_read(FUC_DONE) & 0x40));
return mmio_read(FUC_MMIO_RDVAL);
}
/*---------------------------------------------------------------------------
Writes a byte to the serial port by waiting
---------------------------------------------------------------------------*/
void uart_putc(uint32_t character)
{
if(character == '\n'){
while(!(mmio_read(AUX_MU_LSR_REG) & 0x20));
mmio_write(AUX_MU_IO_REG, '\r');
}
while(!(mmio_read(AUX_MU_LSR_REG) & 0x20));
mmio_write(AUX_MU_IO_REG, character);
} // End uart_putc()
/*------------------------------------------------------------------------------------
* MailboxRead returns the current value in the mailbox addressed to a channel
------------------------------------------------------------------------------------*/
uint32_t MailboxRead(uint32_t channel)
{
UNUSED(channel);
uint32_t message;
do{
while((mmio_read(0x2000B898) & (1 << 30)));
message = mmio_read(0x2000B880);
}while((message & 0xF) != channel);
return message & 0xFFFFFFF0;
} //MailboxRead
void ihbody(void)
{
unsigned int intr = mmio_read(0x08);
if(intr & 0x8){
mmio_write(0x804,mmio_read(0x0804)+1);
}
j++;
mmio_write(0x74,1);
mmio_write(0x04,intr);
}
void mmwr(uint32_t addr, int val, uint32_t u1, uint32_t u2)
{
extr(addr, addr, 2, 25);
mmio_write(FUC_MMIO_WRVAL, val);
mmio_write(FUC_MMIO_CTRL, (addr << 2) |
(u1 & 1) | 0xc0000000 | (!!u2) << 29);
while (mmio_read(FUC_MMIO_CTRL) & 0x80000000);
if (u2)
while (!(mmio_read(FUC_DONE)&0x80));
}
void ihbody1(void)
{
unsigned int intr = mmio_read(0x08);
mmio_write(0x04,0x1);
// if(intr == 0x1){
mmio_write(0x800,mmio_read(0x0800)+1);
// }
k++;
// mmio_write(0x28,1);
}
uint32_t mbox_read(uint8_t channel)
{
while(1)
{
while(mmio_read(MBOX_BASE + MBOX_STATUS) & MBOX_EMPTY);
uint32_t data = mmio_read(MBOX_BASE + MBOX_READ);
uint8_t read_channel = (uint8_t)(data & 0xf);
if(read_channel == channel)
return (data & 0xfffffff0);
}
}
static unsigned int mbox_read(unsigned char channel) {
while (1) {
while (mmio_read(MAIL_BASE + MAIL_STATUS) & MAIL_EMPTY)
;
unsigned int data = mmio_read(MAIL_BASE + MAIL_READ);
unsigned char read_channel = (unsigned char) (data & 0xf);
if (read_channel == channel) {
return (data & 0xfffffff0);
}
}
}
int gpioRead(int pinno)
{
int ireg;
if(pinno >= 32){
pinno = pinno - 32;
ireg = mmio_read(GPLEV1);
}else{
ireg = mmio_read(GPLEV0);
}
return (ireg & (1 << pinno));
}
/*---------------------------------------------------------------------------
Called from an assembly language routine that saves the stack
---------------------------------------------------------------------------*/
void __attribute__((interrupt)) c_irq_handler( void )
{
uint32_t status;
uint32_t data;
while(!((status = mmio_read(AUX_MU_IIR_REG)) & 1)){
if((status & 6) == 4){
data = mmio_read(AUX_MU_IO_REG);
rxbuffer[rxhead] = data;
rxhead++;
if(rxhead > RXBUFMASK){
rxhead = 0;
}
}
}
} // End c_irq_handler()
void uart_init ()
{
mmio_write(IRQ_DISABLE1, 1<<29);
unsigned int ra;
mmio_write(AUX_ENABLES,1);
mmio_write(AUX_MU_IER_REG,0);
mmio_write(AUX_MU_CNTL_REG,0);
mmio_write(AUX_MU_LCR_REG,3);
mmio_write(AUX_MU_MCR_REG,0);
mmio_write(AUX_MU_IER_REG,0x5); //enable rx interrupts
mmio_write(AUX_MU_IIR_REG,0xC6);
mmio_write(AUX_MU_BAUD_REG, 3254); //(250000000/(8*9600))-1
ra=mmio_read(GPFSEL1);
ra&=~(7<<12); //gpio14
ra|=2<<12; //alt5
ra&=~(7<<15); //gpio15
ra|=2<<15; //alt5
mmio_write(GPFSEL1,ra);
mmio_write(GPPUD,0);
mmio_write(GPPUDCLK0,(1<<14)|(1<<15));
mmio_write(GPPUDCLK0,0);
mmio_write(AUX_MU_CNTL_REG,3);
mmio_write(IRQ_ENABLE1, 1<<29);
}
int mailbox_write(unsigned int value, unsigned int channel) {
printk("MAILBOX_WRITE: writing value=%x channel %x\n",
value,channel);
/* Bottom 4 bits of value must be 0 */
if (value&0xf) {
printk("mailbox_write: bottom bits not zero %x\n",
value);
return -1;
}
/* Channel must fit in 4 bits */
if (channel>15) {
printk("mailbox_write: channel too high %x\n",
channel);
return -1;
}
/* Wait until mailbox is ready */
while( (mmio_read(MAILBOX_STATUS) & MAIL_FULL) ) {
printk("Write mailbox full!\n");
}
/* write the command */
mmio_write(MAILBOX_WRITE,channel|value);
return 0;
}
/* Return true if card Software Release is OK */
static bool check_app(struct mdev_ctx *mctx, uint16_t min_rel)
{
int rc;
uint64_t data;
/* Get MMIO_APP_VERSION_REG */
rc = mmio_read(mctx->afu_h, MMIO_MASTER_CTX_NUMBER,
MMIO_APP_VERSION_REG, &data);
if (0 != rc)
return false;
/* Check Application Version for Version higher than 0403 */
/* Register 8 does have following layout for the 64 bits */
/* RRRRFFIINNNNNNNN */
/* RRRR == 16 bit Software Release (0404) */
/* FF == 8 bit Software Fix Level on card (01) */
/* II == 8 bit Software Interface ID (03) */
/* NNNNNNNN == 32 Bit Function (475a4950) = (GZIP) */
if (0x475a4950 != (data & 0xffffffff))
return false;
data = data >> 32; /* RRRRFFII */
if (0x03 == (data & 0xff)) { /* Check II */
data = data >> 16; /* Check RRRR */
if ((uint16_t)data >= min_rel) /* need >= min_rel */
return true;
}
static int lua_mmio_read(lua_State *L) {
mmio_t *mmio;
uint8_t *buf;
uintptr_t offset;
unsigned int i, len;
int ret;
mmio = luaL_checkudata(L, 1, "periphery.MMIO");
lua_mmio_checktype(L, 2, LUA_TNUMBER);
lua_mmio_checktype(L, 3, LUA_TNUMBER);
offset = lua_tounsigned(L, 2);
len = lua_tounsigned(L, 3);
if ((buf = malloc(len)) == NULL)
return lua_mmio_error(L, MMIO_ERROR_ALLOC, errno, "Error: allocating memory");
if ((ret = mmio_read(mmio, offset, buf, len)) < 0) {
free(buf);
return lua_mmio_error(L, ret, mmio_errno(mmio), "Error: %s", mmio_errmsg(mmio));
}
/* Convert byte buffer to byte table */
lua_newtable(L);
for (i = 0; i < len; i++) {
lua_pushunsigned(L, i+1);
lua_pushunsigned(L, buf[i]);
lua_settable(L, -3);
}
free(buf);
return 1;
}
static void
uart_putc(unsigned char byte)
{
// Wait for UART to become ready to transmit.
while ( mmio_read(UART0_FR) & (1 << 5) ) { }
mmio_write(UART0_DR, byte);
}
uint8 SMP::op_read(uint16 addr) {
#if defined(CYCLE_ACCURATE)
tick();
#endif
if((addr & 0xfff0) == 0x00f0) return mmio_read(addr);
if(addr >= 0xffc0 && status.iplrom_enable) return iplrom[addr & 0x3f];
return apuram[addr];
}
int uart_putc(int byte)
{
while(mmio_read(UART0_FR) & (1 << 5))
usleep(2000);
mmio_write(UART0_DR, (uint8_t)(byte & 0xff));
return byte;
}
void uart_putc ( unsigned int c )
{
while(1)
{
if(mmio_read(AUX_MU_LSR_REG)&0x20) break;
}
mmio_write(AUX_MU_IO_REG,c);
}
void gpioSetInput(int no)
{
int pinno=no%10;
int bankno=get_fsel_bank_no(pinno);
int ireg=mmio_read(bankno);
ireg &= ~(1 << (pinno*3));
mmio_write(bankno, ireg);
}
void uart_putc(uint8_t byte) {
// wait for UART to become ready to transmit
while (1) {
if (!(mmio_read(UART0_FR) & (1 << 5))) {
break;
}
}
mmio_write(UART0_DR, byte);
}
/*
* Wait till busy bit is reset
*/
static int rtc_write_wait(void)
{
int i = WRITE_WAIT_MAX_COUNT;
while((mmio_read(AM335X_RTC_BASE+AM335X_RTC_STATUS_REG) & 0x1) && (i--));
if(i == 0)
return RTEMS_RESOURCE_IN_USE;
else
return RTEMS_SUCCESSFUL;
}
uint8 SMP::op_read(uint16 addr, eCDLog_Flags flags) {
#if defined(CYCLE_ACCURATE)
tick();
#endif
if((addr & 0xfff0) == 0x00f0) return mmio_read(addr);
if(addr >= 0xffc0 && status.iplrom_enable) return iplrom[addr & 0x3f];
cdlInfo.currFlags = flags;
cdlInfo.set(eCDLog_AddrType_APURAM, addr);
return apuram[addr];
}
void gpioWriteSafe(int pinno, int level)
{
int regval;
if(pinno >= 32){
pinno = pinno - 32;
regval = mmio_read(GPLEV1);
}else{
regval = mmio_read(GPLEV0);
}
regval |= (1 << pinno);
if(pinno >= 32){
mmio_write(level ? GPSET1 : GPCLR1, regval);
}else{
mmio_write(level ? GPSET0 : GPCLR0, regval);
}
}
void omap3_irq_handle(void) {
/* Function called from assembly to handle interrupts */
/* get irq */
int irq = mmio_read(omap_intr.base + OMAP3_INTCPS_SIR_IRQ) & OMAP3_INTR_ACTIVEIRQ_MASK;
/* handle irq */
irq_handle(irq);
/* re-enable. this should not trigger interrupts due to current cpsr state */
mmio_write(omap_intr.base + OMAP3_INTCPS_CONTROL,OMAP3_INTR_NEWIRQAGR);
}
