void main(void) { timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); tsadc_init(); /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); timestamp_add_now(TS_BEFORE_INITRAM); sdram_init(get_sdram_config()); timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); cbmem_initialize_empty(); timestamp_add_now(TS_END_ROMSTAGE); run_ramstage(); }
static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ exynos5250_config_l2_cache(); mmu_init(); mmu_config_range(0, DRAM_START, DCACHE_OFF); mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF); mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); dcache_invalidate_all(); dcache_mmu_enable(); /* this is going to move, but we must have it now and we're * not sure where */ exception_init(); const unsigned epll_hz = 192000000; const unsigned sample_rate = 48000; const unsigned lr_frame_size = 256; clock_epll_set_rate(epll_hz); clock_select_i2s_clk_source(); clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size); power_enable_xclkout(); }
static void enable_cache(void) { mmu_init(); /* Whole space is uncached. */ mmu_config_range(0, 4096, DCACHE_OFF); /* SRAM is cached. MMU code will round size up to page size. */ mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB), DCACHE_WRITEBACK); mmu_disable_range(0, 1); dcache_mmu_enable(); }
void sdm845_mmu_init(void) { mmu_init(); mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM); mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM); mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM); mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent), UNCACHED_RAM); mmu_enable(); }
void setup_dram_mappings(enum dram_state dram) { if (dram == DRAM_INITIALIZED) { mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); } else { mmu_disable_range(DRAM_START, DRAM_SIZE); /* Map DMA memory */ mmu_disable_range(DMA_START, DMA_SIZE); } }
void setup_dram_mappings(enum dram_state dram) { if (dram == DRAM_INITIALIZED) { mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); /* Mark cbmem backing store as ready. */ ipq_cbmem_backing_store_ready(); } else { mmu_disable_range(DRAM_START, DRAM_SIZE); /* Map DMA memory */ mmu_disable_range(DMA_START, DMA_SIZE); } }
static void __attribute__((noinline)) romstage(void) { timestamp_init(0); timestamp_add_now(TS_START_ROMSTAGE); console_init(); exception_init(); sdram_init(get_sdram_config()); /* used for MMU and CBMEM setup, in MB */ u32 dram_start_mb = (uintptr_t)_dram/MiB; u32 dram_end_mb = sdram_max_addressable_mb(); u32 dram_size_mb = dram_end_mb - dram_start_mb; configure_l2_cache(); mmu_init(); /* Device memory below DRAM is uncached. */ mmu_config_range(0, dram_start_mb, DCACHE_OFF); /* SRAM is cached. MMU code will round size up to page size. */ mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB), DCACHE_WRITEBACK); /* DRAM is cached. */ mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK); /* A window for DMA is uncached. */ mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); /* The space above DRAM is uncached. */ if (dram_end_mb < 4096) mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF); mmu_disable_range(0, 1); dcache_mmu_enable(); /* * A watchdog reset only resets part of the system so it ends up in * a funny state. If that happens, we need to reset the whole machine. */ if (power_reset_status() == POWER_RESET_WATCHDOG) { printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n"); hard_reset(); } /* FIXME: this may require coordination with moving timestamps */ cbmem_initialize_empty(); early_mainboard_init(); run_ramstage(); }
void main(void) { #if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = timestamp_get(); start_romstage_time = timestamp_get(); #endif console_init(); configure_l2ctlr(); tsadc_init(); /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS before_dram_time = timestamp_get(); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS after_dram_time = timestamp_get(); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time); timestamp_add(TS_BEFORE_INITRAM, before_dram_time); timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif #if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) void *entry = vboot2_load_ramstage(); if (entry != NULL) stage_exit(entry); #endif run_ramstage(); }
void setup_mmu(enum dram_state dram) { dcache_mmu_disable(); /* start with mapping everything as strongly ordered. */ mmu_config_range(0, 4096, DCACHE_OFF); /* Map Device memory. */ mmu_config_range_kb(RPM_START, RPM_SIZE, DCACHE_OFF); mmu_config_range_kb(SRAM_START, SRAM_END - SRAM_START, DCACHE_WRITEBACK); /* Map DRAM memory */ setup_dram_mappings(dram); mmu_disable_range(DRAM_END, 4096 - DRAM_END); /* disable Page 0 for trapping NULL pointer references. */ mmu_disable_range_kb(0, 1); mmu_init(); dcache_mmu_enable(); }
void platform_romstage_main(void) { tsadc_init(TSHUT_POL_HIGH); /* Init DVS to conservative values. */ init_dvs_outputs(); prepare_sdmmc(); prepare_usb(); sdram_init(get_sdram_config()); mmu_config_range((void *)0, (uintptr_t)sdram_size_mb() * MiB, CACHED_MEM); mmu_config_range(_dma_coherent, REGION_SIZE(dma_coherent), UNCACHED_MEM); }
void mt8173_mmu_init(void) { mmu_init(); /* Set 0x0 to the end of 2GB dram address as device memory */ mmu_config_range((void *)0, (uintptr_t)_dram + 2U * GiB, DEV_MEM); /* SRAM is cached */ mmu_config_range(_sram_l2c, _sram_l2c_size + _sram_size, CACHED_MEM); /* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */ mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM); /* set ttb as secure */ mmu_config_range(_ttb, _ttb_size, SECURE_MEM); mmu_enable(); }
void main(void) { console_init(); tsadc_init(TSHUT_POL_HIGH); exception_init(); /* Init DVS to conservative values. */ init_dvs_outputs(); prepare_usb(); sdram_init(get_sdram_config()); mmu_config_range((void *)0, (uintptr_t)dram_size, CACHED_MEM); mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM); cbmem_initialize_empty(); run_ramstage(); }
void bootblock_soc_init(void) { if (get_wakeup_state() == WAKEUP_DIRECT) { wakeup(); /* Never returns. */ } /* set up dcache and MMU */ mmu_init(); mmu_disable_range(0, SRAM_START); mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK); mmu_config_range(SRAM_END, 4096 - SRAM_END, DCACHE_OFF); dcache_mmu_enable(); /* For most ARM systems, we have to initialize firmware media source * (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is * already handled by iROM so there's no need to setup again. */ }
void mt8173_mmu_after_dram(void) { /* Map DRAM as cached now that it's up and running */ mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM); /* Unmap L2C SRAM so it can be reclaimed by L2 cache */ /* TODO: Implement true unmapping, and also use it for the zero-page! */ mmu_config_range(_sram_l2c, _sram_l2c_size, DEV_MEM); mmu_config_range(_dram_dma, _dram_dma_size, UNCACHED_MEM); /* Careful: changing cache geometry while it's active is a bad idea! */ mmu_disable(); /* Return L2C SRAM back to L2 cache. Set it to 512KiB which is the max * available L2 cache for A53 in MT8173. */ write32(&mt8173_mcucfg->mp0_ca7l_cache_config, 3 << 8); /* turn off the l2c sram clock */ write32(&mt8173_infracfg->infra_pdn0, L2C_SRAM_PDN); /* Reenable MMU with now enlarged L2 cache. Page tables still valid. */ mmu_enable(); }
static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ exynos5250_config_l2_cache(); mmu_init(); mmu_config_range(0, DRAM_START, DCACHE_OFF); mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); dcache_mmu_enable(); const unsigned epll_hz = 192000000; const unsigned sample_rate = 48000; const unsigned lr_frame_size = 256; clock_epll_set_rate(epll_hz); clock_select_i2s_clk_source(); clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size); power_enable_xclkout(); }
void bootblock_soc_init(void) { rkclk_init(); mmu_init(); /* Start with a clean slate. */ mmu_config_range(0, 4096, DCACHE_OFF); /* SRAM is tightly wedged between registers, need to use subtables. Map * write-through as equivalent for non-cacheable without XN on A17. */ mmu_config_range_kb((uintptr_t)_sram/KiB, _sram_size/KiB, DCACHE_WRITETHROUGH); dcache_mmu_enable(); rkclk_configure_crypto(148500*KHz); }
void rk_display_init(device_t dev, u32 lcdbase, unsigned long fb_size) { struct edid edid; struct soc_rockchip_rk3288_config *conf = dev->chip_info; uint32_t lower = ALIGN_DOWN(lcdbase, MiB); uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB); enum vop_modes detected_mode = VOP_MODE_UNKNOWN; printk(BIOS_SPEW, "LCD framebuffer @%p\n", (void *)(lcdbase)); memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ dcache_clean_invalidate_by_mva((void *)lower, upper - lower); mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF); switch (conf->vop_mode) { case VOP_MODE_NONE: return; case VOP_MODE_AUTO_DETECT: /* try EDP first, then HDMI */ case VOP_MODE_EDP: printk(BIOS_DEBUG, "Attempting to setup EDP display.\n"); rkclk_configure_edp(); rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz); rk_edp_init(conf->vop_id); if (rk_edp_get_edid(&edid) == 0) { detected_mode = VOP_MODE_EDP; break; } else { printk(BIOS_WARNING, "Cannot get EDID from EDP.\n"); if (conf->vop_mode == VOP_MODE_EDP) return; } /* fall thru */ case VOP_MODE_HDMI: printk(BIOS_DEBUG, "Attempting to setup HDMI display.\n"); rkclk_configure_hdmi(); rkclk_configure_vop_aclk(conf->vop_id, 384 * MHz); rk_hdmi_init(conf->vop_id); if (rk_hdmi_get_edid(&edid) == 0) { detected_mode = VOP_MODE_HDMI; break; } else { printk(BIOS_WARNING, "Cannot get EDID from HDMI.\n"); if (conf->vop_mode == VOP_MODE_HDMI) return; } /* fall thru */ default: printk(BIOS_WARNING, "Cannot read any edid info, aborting.\n"); return; } if (rkclk_configure_vop_dclk(conf->vop_id, edid.pixel_clock * KHz)) { printk(BIOS_WARNING, "config vop err\n"); return; } edid.framebuffer_bits_per_pixel = conf->framebuffer_bits_per_pixel; edid.bytes_per_line = edid.ha * conf->framebuffer_bits_per_pixel / 8; edid.x_resolution = edid.ha; edid.y_resolution = edid.va; rkvop_mode_set(conf->vop_id, &edid, detected_mode); rkvop_enable(conf->vop_id, lcdbase, &edid); switch (detected_mode) { case VOP_MODE_HDMI: if (rk_hdmi_enable(&edid)) { printk(BIOS_WARNING, "hdmi enable err\n"); return; } /* * HACK: if we do remove this delay, HDMI TV may not show * anythings. So we make an delay here, ensure TV have * enough time to respond. */ mdelay(2000); break; case VOP_MODE_EDP: default: if (rk_edp_enable()) { printk(BIOS_WARNING, "edp enable err\n"); return; } mainboard_power_on_backlight(); break; } set_vbe_mode_info_valid(&edid, (uintptr_t)lcdbase); }
/* this is really aimed at the lcd panel. That said, there are two display * devices on this part and we may someday want to extend it for other boards. */ void display_startup(device_t dev) { struct soc_nvidia_tegra124_config *config = dev->chip_info; struct display_controller *disp_ctrl = (void *)config->display_controller; struct pwm_controller *pwm = (void *)TEGRA_PWM_BASE; struct tegra_dc *dc = &dc_data; u32 plld_rate; /* init dc */ dc->base = (void *)TEGRA_ARM_DISPLAYA; dc->config = config; config->dc_data = dc; /* Note dp_init may read EDID and change some config values. */ dp_init(config); /* should probably just make it all MiB ... in future */ u32 framebuffer_size_mb = config->framebuffer_size / MiB; u32 framebuffer_base_mb= config->framebuffer_base / MiB; /* light it all up */ /* This one may have been done in romstage but that's ok for now. */ if (config->panel_vdd_gpio){ gpio_output(config->panel_vdd_gpio, 1); printk(BIOS_SPEW,"%s: panel_vdd setting gpio %08x to %d\n", __func__, config->panel_vdd_gpio, 1); } udelay(config->vdd_delay_ms * 1000); if (config->backlight_vdd_gpio){ gpio_output(config->backlight_vdd_gpio, 1); printk(BIOS_SPEW,"%s: backlight vdd setting gpio %08x to %d\n", __func__, config->backlight_vdd_gpio, 1); } if (config->lvds_shutdown_gpio){ gpio_output(config->lvds_shutdown_gpio, 0); printk(BIOS_SPEW,"%s: lvds shutdown setting gpio %08x to %d\n", __func__, config->lvds_shutdown_gpio, 0); } if (framebuffer_size_mb == 0){ framebuffer_size_mb = ALIGN_UP(config->xres * config->yres * (config->framebuffer_bits_per_pixel / 8), MiB)/MiB; } if (! framebuffer_base_mb) framebuffer_base_mb = fb_base_mb(); config->framebuffer_size = framebuffer_size_mb * MiB; config->framebuffer_base = framebuffer_base_mb * MiB; mmu_config_range(framebuffer_base_mb, framebuffer_size_mb, config->cache_policy); printk(BIOS_SPEW, "LCD frame buffer at %dMiB to %dMiB\n", framebuffer_base_mb, framebuffer_base_mb + framebuffer_size_mb); /* GPIO magic here if needed to start powering up things. You * really only want to enable vdd, wait a bit, and then enable * the panel. However ... the timings in the tegra20 dts make * no sense to me. I'm pretty sure they're wrong. * The panel_vdd is done in the romstage, so we need only * light things up here once we're sure it's all working. */ /* The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the * update_display_mode() for detail. */ plld_rate = clock_display(config->pixel_clock * 2); if (plld_rate == 0) { printk(BIOS_ERR, "dc: clock init failed\n"); return; } else if (plld_rate != config->pixel_clock * 2) { printk(BIOS_WARNING, "dc: plld rounded to %u\n", plld_rate); config->pixel_clock = plld_rate / 2; } /* Init dc */ if (tegra_dc_init(disp_ctrl)) { printk(BIOS_ERR, "dc: init failed\n"); return; } /* Configure dc mode */ if (update_display_mode(disp_ctrl, config)) { printk(BIOS_ERR, "dc: failed to configure display mode.\n"); return; } /* Enable dp */ dp_enable(dc->out); /* Init frame buffer */ memset((void *)(framebuffer_base_mb*MiB), 0x00, framebuffer_size_mb*MiB); update_window(disp_ctrl, config); /* Set up Tegra PWM n (where n is specified in config->pwm) to drive the * panel backlight. */ printk(BIOS_SPEW, "%s: enable panel backlight pwm\n", __func__); WRITEL(((1 << NV_PWM_CSR_ENABLE_SHIFT) | (220 << NV_PWM_CSR_PULSE_WIDTH_SHIFT) | /* 220/256 */ 0x02e), /* frequency divider */ &pwm->pwm[config->pwm].csr); udelay(config->pwm_to_bl_delay_ms * 1000); if (config->backlight_en_gpio){ gpio_output(config->backlight_en_gpio, 1); printk(BIOS_SPEW,"%s: backlight enable setting gpio %08x to %d\n", __func__, config->backlight_en_gpio, 1); } printk(BIOS_INFO, "%s: display init done.\n", __func__); /* tell depthcharge ... */ struct edid edid; edid.bytes_per_line = ((config->xres * config->framebuffer_bits_per_pixel / 8 + 31) / 32 * 32); edid.x_resolution = edid.bytes_per_line / (config->framebuffer_bits_per_pixel / 8); edid.y_resolution = config->yres; edid.framebuffer_bits_per_pixel = config->framebuffer_bits_per_pixel; set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB)); }
/* this happens after cpu_init where exynos resources are set */ static void mainboard_init(device_t dev) { int dp_tries; struct s5p_dp_device dp_device = { .base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE, .video_info = &dp_video_info, }; void *fb_addr = (void *)(get_fb_base_kb() * KiB); gpio_init(); i2c_init(TPS65090_BUS, I2C_0_SPEED, I2C_SLAVE); i2c_init(7, I2C_0_SPEED, I2C_SLAVE); tmu_init(&exynos5250_tmu_info); /* Clock Gating all the unused IP's to save power */ clock_gate(); /* Disable USB3.0 PLL to save 250mW of power */ disable_usb30_pll(); set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); lcd_vdd(); // FIXME: should timeout do { udelay(50); } while (!exynos_dp_hotplug()); exynos_dp_bridge_setup(); for (dp_tries = 1; dp_tries <= MAX_DP_TRIES; dp_tries++) { exynos_dp_bridge_init(); if (exynos_dp_hotplug()) { exynos_dp_reset(); continue; } if (dp_controller_init(&dp_device)) continue; udelay(LCD_T3_DELAY_MS * 1000); backlight_vdd(); backlight_pwm(); backlight_en(); /* if we're here, we're successful */ break; } if (dp_tries > MAX_DP_TRIES) printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__); // Uncomment to get excessive GPIO output: // gpio_info(); } static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ exynos5250_config_l2_cache(); mmu_init(); mmu_config_range(0, DRAM_START, DCACHE_OFF); mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); dcache_invalidate_all(); dcache_mmu_enable(); /* this is going to move, but we must have it now and we're * not sure where */ exception_init(); const unsigned epll_hz = 192000000; const unsigned sample_rate = 48000; const unsigned lr_frame_size = 256; clock_epll_set_rate(epll_hz); clock_select_i2s_clk_source(); clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size); power_enable_xclkout(); }