Пример #1
0
static int mvneta_probe(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);
	struct mvneta_port *pp = dev_get_priv(dev);
	void *blob = (void *)gd->fdt_blob;
	int node = dev->of_offset;
	struct mii_dev *bus;
	unsigned long addr;
	void *bd_space;

	/*
	 * Allocate buffer area for descs and rx_buffers. This is only
	 * done once for all interfaces. As only one interface can
	 * be active. Make this area DMA save by disabling the D-cache
	 */
	if (!buffer_loc.tx_descs) {
		/* Align buffer area for descs and rx_buffers to 1MiB */
		bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
		mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE,
						DCACHE_OFF);
		buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
		buffer_loc.rx_descs = (struct mvneta_rx_desc *)
			((phys_addr_t)bd_space +
			 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc));
		buffer_loc.rx_buffers = (phys_addr_t)
			(bd_space +
			 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) +
			 MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc));
	}

	pp->base = (void __iomem *)pdata->iobase;

	/* Configure MBUS address windows */
	if (of_device_is_compatible(dev, "marvell,armada-3700-neta"))
		mvneta_bypass_mbus_windows(pp);
	else
		mvneta_conf_mbus_windows(pp);

	/* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
	pp->phy_interface = pdata->phy_interface;

	/* Now read phyaddr from DT */
	addr = fdtdec_get_int(blob, node, "phy", 0);
	addr = fdt_node_offset_by_phandle(blob, addr);
	pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);

	bus = mdio_alloc();
	if (!bus) {
		printf("Failed to allocate MDIO bus\n");
		return -ENOMEM;
	}

	bus->read = mvneta_mdio_read;
	bus->write = mvneta_mdio_write;
	snprintf(bus->name, sizeof(bus->name), dev->name);
	bus->priv = (void *)pp;
	pp->bus = bus;

	return mdio_register(bus);
}
Пример #2
0
void lcd_ctrl_init(void *lcdbase)
{
	int type = DCACHE_OFF;
	int size;

	assert(disp_config);

	/* Make sure that we can acommodate the selected LCD */
	assert(disp_config->width <= LCD_MAX_WIDTH);
	assert(disp_config->height <= LCD_MAX_HEIGHT);
	assert(disp_config->log2_bpp <= LCD_MAX_LOG2_BPP);
	if (disp_config->width <= LCD_MAX_WIDTH
			&& disp_config->height <= LCD_MAX_HEIGHT
			&& disp_config->log2_bpp <= LCD_MAX_LOG2_BPP)
		update_panel_size(disp_config);
	size = lcd_get_size(&lcd_line_length);

	/* Set up the LCD caching as requested */
	if (config.cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
		type = DCACHE_WRITETHROUGH;
	else if (config.cache_type & FDT_LCD_CACHE_WRITE_BACK)
		type = DCACHE_WRITEBACK;
	mmu_set_region_dcache_behaviour(disp_config->frame_buffer, size, type);

	/* Enable flushing after LCD writes if requested */
	lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH);

	debug("LCD frame buffer at %08X\n", disp_config->frame_buffer);
}
Пример #3
0
static int tegra_lcd_probe(struct udevice *dev)
{
    struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
    struct video_priv *uc_priv = dev_get_uclass_priv(dev);
    struct tegra_lcd_priv *priv = dev_get_priv(dev);
    const void *blob = gd->fdt_blob;
    int type = DCACHE_OFF;

    /* Initialize the Tegra display controller */
    if (tegra_display_probe(blob, priv, (void *)plat->base)) {
        printf("%s: Failed to probe display driver\n", __func__);
        return -1;
    }

    tegra_lcd_check_next_stage(blob, priv, 1);

    /* Set up the LCD caching as requested */
    if (priv->cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
        type = DCACHE_WRITETHROUGH;
    else if (priv->cache_type & FDT_LCD_CACHE_WRITE_BACK)
        type = DCACHE_WRITEBACK;
    mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size, type);

    /* Enable flushing after LCD writes if requested */
    video_set_flush_dcache(dev, priv->cache_type & FDT_LCD_CACHE_FLUSH);

    uc_priv->xsize = priv->width;
    uc_priv->ysize = priv->height;
    uc_priv->bpix = priv->log2_bpp;
    debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer,
          plat->size);

    return 0;
}
Пример #4
0
static int zynq_gem_probe(struct udevice *dev)
{
	void *bd_space;
	struct zynq_gem_priv *priv = dev_get_priv(dev);
	int ret;

	/* Align rxbuffers to ARCH_DMA_MINALIGN */
	priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
	memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);

	/* Align bd_space to MMU_SECTION_SHIFT */
	bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
	mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
					BD_SPACE, DCACHE_OFF);

	/* Initialize the bd spaces for tx and rx bd's */
	priv->tx_bd = (struct emac_bd *)bd_space;
	priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);

	priv->bus = mdio_alloc();
	priv->bus->read = zynq_gem_miiphy_read;
	priv->bus->write = zynq_gem_miiphy_write;
	priv->bus->priv = priv;
	strcpy(priv->bus->name, "gem");

	ret = mdio_register(priv->bus);
	if (ret)
		return ret;

	zynq_phy_init(dev);

	return 0;
}
Пример #5
0
int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
			int phy_addr, u32 emio)
{
	struct eth_device *dev;
	struct zynq_gem_priv *priv;
	void *bd_space;

	dev = calloc(1, sizeof(*dev));
	if (dev == NULL)
		return -1;

	dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
	if (dev->priv == NULL) {
		free(dev);
		return -1;
	}
	priv = dev->priv;

	/* Align rxbuffers to ARCH_DMA_MINALIGN */
	priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
	memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);

	/* Align bd_space to MMU_SECTION_SHIFT */
	bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
	mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
					BD_SPACE, DCACHE_OFF);

	/* Initialize the bd spaces for tx and rx bd's */
	priv->tx_bd = (struct emac_bd *)bd_space;
	priv->rx_bd = (struct emac_bd *)((unsigned long)bd_space +
					 BD_SEPRN_SPACE);

	priv->phyaddr = phy_addr;
	priv->emio = emio;

#ifndef CONFIG_ZYNQ_GEM_INTERFACE
	priv->interface = PHY_INTERFACE_MODE_MII;
#else
	priv->interface = CONFIG_ZYNQ_GEM_INTERFACE;
#endif

	sprintf(dev->name, "Gem.%lx", base_addr);

	dev->iobase = base_addr;

	dev->init = zynq_gem_init;
	dev->halt = zynq_gem_halt;
	dev->send = zynq_gem_send;
	dev->recv = zynq_gem_recv;
	dev->write_hwaddr = zynq_gem_setup_mac;

	eth_register(dev);

	miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
	priv->bus = miiphy_get_dev_by_name(dev->name);

	return 1;
}
Пример #6
0
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
	enum dcache_option option = DCACHE_WRITETHROUGH;
#else
	enum dcache_option option = DCACHE_WRITEBACK;
#endif
	/* Avoid random hang when download by usb */
	invalidate_dcache_all();

	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();

	/* Enable caching on OCRAM and ROM */
	mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
					ROMCP_ARB_END_ADDR,
					option);
	mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
					IRAM_SIZE,
					option);
}
Пример #7
0
void noncached_init(void)
{
	phys_addr_t start, end;
	size_t size;

	end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
	size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
	start = end - size;

	debug("mapping memory %pa-%pa non-cached\n", &start, &end);

	noncached_start = start;
	noncached_end = end;
	noncached_next = start;

#ifndef CONFIG_SYS_DCACHE_OFF
	mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
#endif
}
Пример #8
0
static int zynq_gem_probe(struct udevice *dev)
{
	void *bd_space;
	struct zynq_gem_priv *priv = dev_get_priv(dev);
	int ret;

	/* Align rxbuffers to ARCH_DMA_MINALIGN */
	priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
	if (!priv->rxbuffers)
		return -ENOMEM;

	memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);

	/* Align bd_space to MMU_SECTION_SHIFT */
	bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
	if (!bd_space)
		return -ENOMEM;

	mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
					BD_SPACE, DCACHE_OFF);

	/* Initialize the bd spaces for tx and rx bd's */
	priv->tx_bd = (struct emac_bd *)bd_space;
	priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);

	ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
	if (ret < 0) {
		dev_err(dev, "failed to get clock\n");
		return -EINVAL;
	}

	priv->bus = mdio_alloc();
	priv->bus->read = zynq_gem_miiphy_read;
	priv->bus->write = zynq_gem_miiphy_write;
	priv->bus->priv = priv;

	ret = mdio_register_seq(priv->bus, dev->seq);
	if (ret)
		return ret;

	return zynq_phy_init(dev);
}