void init_main_ppm(uint32_t period, uint32_t out_enable)
{
register Pwm *pwmptr ;
setupPulsesPPM(EXTERNAL_MODULE) ;
if (out_enable) {
module_output_active();
}
pwmptr = PWM ;
// PWM3 for PPM output
pwmptr->PWM_CH_NUM[3].PWM_CMR = 0x0004000B ; // CLKA
if (!g_model.moduleData[EXTERNAL_MODULE].ppmPulsePol) {
pwmptr->PWM_CH_NUM[3].PWM_CMR |= 0x00000200 ; // CPOL
}
pwmptr->PWM_CH_NUM[3].PWM_CPDR = period ; // Period in half uS
pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period ; // Period in half uS
pwmptr->PWM_CH_NUM[3].PWM_CDTY = g_model.moduleData[EXTERNAL_MODULE].ppmDelay*100+600; // Duty in half uS
pwmptr->PWM_CH_NUM[3].PWM_CDTYUPD = g_model.moduleData[EXTERNAL_MODULE].ppmDelay*100+600; // Duty in half uS
pwmptr->PWM_ENA = PWM_ENA_CHID3 ; // Enable channel 3
pwmptr->PWM_IER1 = PWM_IER1_CHID3 ;
NVIC_SetPriority(PWM_IRQn, 3 ) ;
NVIC_EnableIRQ(PWM_IRQn) ;
}
void init_main_ppm( uint32_t period, uint32_t out_enable )
{
register Pwm *pwmptr ;
perOut(g_chans512, 0) ;
setupPulsesPPM() ;
if ( out_enable )
{
module_output_active() ;
}
pwmptr = PWM ;
// PWM3 for PPM output
pwmptr->PWM_CH_NUM[3].PWM_CMR = 0x0004000B ; // CLKA
if (g_model.pulsePol == 0)
{
pwmptr->PWM_CH_NUM[3].PWM_CMR |= 0x00000200 ; // CPOL
}
pwmptr->PWM_CH_NUM[3].PWM_CPDR = period ; // Period in half uS
pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period ; // Period in half uS
pwmptr->PWM_CH_NUM[3].PWM_CDTY = g_model.ppmDelay*100+600 ; // Duty in half uS
pwmptr->PWM_CH_NUM[3].PWM_CDTYUPD = g_model.ppmDelay*100+600 ; // Duty in half uS
pwmptr->PWM_ENA = PWM_ENA_CHID3 ; // Enable channel 3
pwmptr->PWM_IER1 = PWM_IER1_CHID3 ;
#ifdef REVB
configure_pins( PIO_PC15, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_NO_PULLUP ) ;
#endif
#ifdef REVB
// PWM1 for PPM2
pwmptr->PWM_CH_NUM[1].PWM_CMR = 0x0000000B ; // CLKB
if (g_model.pulsePol == 0)
{
pwmptr->PWM_CH_NUM[1].PWM_CMR |= 0x00000200 ; // CPOL
}
pwmptr->PWM_CH_NUM[1].PWM_CPDR = period ; // Period
pwmptr->PWM_CH_NUM[1].PWM_CPDRUPD = period ; // Period
pwmptr->PWM_CH_NUM[1].PWM_CDTY = g_model.ppmDelay*100+600 ; // Duty
pwmptr->PWM_CH_NUM[1].PWM_CDTYUPD = g_model.ppmDelay*100+600 ; // Duty
pwmptr->PWM_ENA = PWM_ENA_CHID1 ; // Enable channel 1
#endif
pwmptr->PWM_IER1 = PWM_IER1_CHID1 ;
NVIC_SetPriority(PWM_IRQn, 3 ) ;
NVIC_EnableIRQ(PWM_IRQn) ;
}
void init_main_ppm(uint32_t period, uint32_t out_enable)
{
register Pwm *pwmptr ;
setupPulsesPPM(EXTERNAL_MODULE) ;
if (out_enable) {
module_output_active();
}
pwmptr = PWM ;
// PWM3 for PPM output
pwmptr->PWM_CH_NUM[3].PWM_CMR = 0x0004000B ; // CLKA
if (!g_model.moduleData[EXTERNAL_MODULE].ppmPulsePol) {
pwmptr->PWM_CH_NUM[3].PWM_CMR |= 0x00000200 ; // CPOL
}
pwmptr->PWM_CH_NUM[3].PWM_CPDR = period ; // Period in half uS
pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period ; // Period in half uS
pwmptr->PWM_CH_NUM[3].PWM_CDTY = g_model.moduleData[EXTERNAL_MODULE].ppmDelay*100+600; // Duty in half uS
pwmptr->PWM_CH_NUM[3].PWM_CDTYUPD = g_model.moduleData[EXTERNAL_MODULE].ppmDelay*100+600; // Duty in half uS
pwmptr->PWM_ENA = PWM_ENA_CHID3 ; // Enable channel 3
pwmptr->PWM_IER1 = PWM_IER1_CHID3 ;
#if !defined(REVA)
// PWM1 for PPM2
configure_pins(PIO_PC15, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_NO_PULLUP ) ;
pwmptr->PWM_CH_NUM[1].PWM_CMR = 0x0000000B ; // CLKB
if (!g_model.moduleData[EXTRA_MODULE].ppmPulsePol) {
pwmptr->PWM_CH_NUM[1].PWM_CMR |= 0x00000200 ; // CPOL
}
pwmptr->PWM_CH_NUM[1].PWM_CPDR = period ; // Period
pwmptr->PWM_CH_NUM[1].PWM_CPDRUPD = period ; // Period
pwmptr->PWM_CH_NUM[1].PWM_CDTY = g_model.moduleData[EXTRA_MODULE].ppmDelay*100+600 ; // Duty
pwmptr->PWM_CH_NUM[1].PWM_CDTYUPD = g_model.moduleData[EXTRA_MODULE].ppmDelay*100+600 ; // Duty
pwmptr->PWM_ENA = PWM_ENA_CHID1 ; // Enable channel 1
pwmptr->PWM_IER1 = PWM_IER1_CHID1 ;
#endif
NVIC_SetPriority(PWM_IRQn, 3 ) ;
NVIC_EnableIRQ(PWM_IRQn) ;
}
