/* * dtrace_xcall() is not called from probe context. */ void dtrace_xcall(processorid_t cpu, dtrace_xcall_t f, void *arg) { xcArg_t xcArg; xcArg.cpu = cpu; xcArg.f = f; xcArg.arg = arg; if (cpu == DTRACE_CPUALL) { mp_cpus_call (CPUMASK_ALL, ASYNC, xcRemote, (void*)&xcArg); } else { mp_cpus_call (cpu_to_cpumask((cpu_t)cpu), ASYNC, xcRemote, (void*)&xcArg); } }
void timer_call_nosync_cpu(int cpu, void (*fn)(void *), void *arg) { /* XXX Needs error checking and retry */ mp_cpus_call(cpu_to_cpumask(cpu), NOSYNC, fn, arg); }
void timer_call_cpu(int cpu, void (*fn)(void *), void *arg) { mp_cpus_call(cpu_to_cpumask(cpu), SYNC, fn, arg); }
int diagCall64(x86_saved_state_t * state) { uint64_t curpos, i, j; uint64_t selector, data; uint64_t currNap, durNap; x86_saved_state64_t *regs; boolean_t diagflag; uint32_t rval = 0; assert(is_saved_state64(state)); regs = saved_state64(state); diagflag = ((dgWork.dgFlags & enaDiagSCs) != 0); selector = regs->rdi; switch (selector) { /* Select the routine */ case dgRuptStat: /* Suck Interruption statistics */ (void) ml_set_interrupts_enabled(TRUE); data = regs->rsi; /* Get the number of processors */ if (data == 0) { /* If no location is specified for data, clear all * counts */ for (i = 0; i < real_ncpus; i++) { /* Cycle through * processors */ for (j = 0; j < 256; j++) cpu_data_ptr[i]->cpu_hwIntCnt[j] = 0; } lastRuptClear = mach_absolute_time(); /* Get the time of clear */ rval = 1; /* Normal return */ break; } (void) copyout((char *) &real_ncpus, data, sizeof(real_ncpus)); /* Copy out number of * processors */ currNap = mach_absolute_time(); /* Get the time now */ durNap = currNap - lastRuptClear; /* Get the last interval * duration */ if (durNap == 0) durNap = 1; /* This is a very short time, make it * bigger */ curpos = data + sizeof(real_ncpus); /* Point to the next * available spot */ for (i = 0; i < real_ncpus; i++) { /* Move 'em all out */ (void) copyout((char *) &durNap, curpos, 8); /* Copy out the time * since last clear */ (void) copyout((char *) &cpu_data_ptr[i]->cpu_hwIntCnt, curpos + 8, 256 * sizeof(uint32_t)); /* Copy out interrupt * data for this * processor */ curpos = curpos + (256 * sizeof(uint32_t) + 8); /* Point to next out put * slot */ } rval = 1; break; case dgPowerStat: { uint32_t c2l = 0, c2h = 0, c3l = 0, c3h = 0, c6l = 0, c6h = 0, c7l = 0, c7h = 0; uint32_t pkg_unit_l = 0, pkg_unit_h = 0, pkg_ecl = 0, pkg_ech = 0; pkg_energy_statistics_t pkes; core_energy_stat_t cest; bzero(&pkes, sizeof(pkes)); bzero(&cest, sizeof(cest)); pkes.pkes_version = 1ULL; rdmsr_carefully(MSR_IA32_PKG_C2_RESIDENCY, &c2l, &c2h); rdmsr_carefully(MSR_IA32_PKG_C3_RESIDENCY, &c3l, &c3h); rdmsr_carefully(MSR_IA32_PKG_C6_RESIDENCY, &c6l, &c6h); rdmsr_carefully(MSR_IA32_PKG_C7_RESIDENCY, &c7l, &c7h); pkes.pkg_cres[0][0] = ((uint64_t)c2h << 32) | c2l; pkes.pkg_cres[0][1] = ((uint64_t)c3h << 32) | c3l; pkes.pkg_cres[0][2] = ((uint64_t)c6h << 32) | c6l; pkes.pkg_cres[0][3] = ((uint64_t)c7h << 32) | c7l; uint32_t cpumodel = cpuid_info()->cpuid_model; boolean_t c8avail; switch (cpumodel) { case CPUID_MODEL_HASWELL_ULT: c8avail = TRUE; break; default: c8avail = FALSE; break; } uint64_t c8r = ~0ULL, c9r = ~0ULL, c10r = ~0ULL; if (c8avail) { rdmsr64_carefully(MSR_IA32_PKG_C8_RESIDENCY, &c8r); rdmsr64_carefully(MSR_IA32_PKG_C9_RESIDENCY, &c9r); rdmsr64_carefully(MSR_IA32_PKG_C10_RESIDENCY, &c10r); } pkes.pkg_cres[0][4] = c8r; pkes.pkg_cres[0][5] = c9r; pkes.pkg_cres[0][6] = c10r; pkes.ddr_energy = ~0ULL; rdmsr64_carefully(MSR_IA32_DDR_ENERGY_STATUS, &pkes.ddr_energy); pkes.llc_flushed_cycles = ~0ULL; rdmsr64_carefully(MSR_IA32_LLC_FLUSHED_RESIDENCY_TIMER, &pkes.llc_flushed_cycles); pkes.ring_ratio_instantaneous = ~0ULL; rdmsr64_carefully(MSR_IA32_RING_PERF_STATUS, &pkes.ring_ratio_instantaneous); pkes.IA_frequency_clipping_cause = ~0ULL; rdmsr64_carefully(MSR_IA32_IA_PERF_LIMIT_REASONS, &pkes.IA_frequency_clipping_cause); pkes.GT_frequency_clipping_cause = ~0ULL; rdmsr64_carefully(MSR_IA32_GT_PERF_LIMIT_REASONS, &pkes.GT_frequency_clipping_cause); rdmsr_carefully(MSR_IA32_PKG_POWER_SKU_UNIT, &pkg_unit_l, &pkg_unit_h); rdmsr_carefully(MSR_IA32_PKG_ENERGY_STATUS, &pkg_ecl, &pkg_ech); pkes.pkg_power_unit = ((uint64_t)pkg_unit_h << 32) | pkg_unit_l; pkes.pkg_energy = ((uint64_t)pkg_ech << 32) | pkg_ecl; rdmsr_carefully(MSR_IA32_PP0_ENERGY_STATUS, &pkg_ecl, &pkg_ech); pkes.pp0_energy = ((uint64_t)pkg_ech << 32) | pkg_ecl; rdmsr_carefully(MSR_IA32_PP1_ENERGY_STATUS, &pkg_ecl, &pkg_ech); pkes.pp1_energy = ((uint64_t)pkg_ech << 32) | pkg_ecl; pkes.pkg_idle_exits = current_cpu_datap()->lcpu.package->package_idle_exits; pkes.ncpus = real_ncpus; (void) ml_set_interrupts_enabled(TRUE); copyout(&pkes, regs->rsi, sizeof(pkes)); curpos = regs->rsi + sizeof(pkes); mp_cpus_call(CPUMASK_ALL, ASYNC, cpu_powerstats, NULL); for (i = 0; i < real_ncpus; i++) { (void) ml_set_interrupts_enabled(FALSE); cest.caperf = cpu_data_ptr[i]->cpu_aperf; cest.cmperf = cpu_data_ptr[i]->cpu_mperf; cest.ccres[0] = cpu_data_ptr[i]->cpu_c3res; cest.ccres[1] = cpu_data_ptr[i]->cpu_c6res; cest.ccres[2] = cpu_data_ptr[i]->cpu_c7res; bcopy(&cpu_data_ptr[i]->cpu_rtimes[0], &cest.crtimes[0], sizeof(cest.crtimes)); bcopy(&cpu_data_ptr[i]->cpu_itimes[0], &cest.citimes[0], sizeof(cest.citimes)); cest.citime_total = cpu_data_ptr[i]->cpu_itime_total; cest.crtime_total = cpu_data_ptr[i]->cpu_rtime_total; cest.cpu_idle_exits = cpu_data_ptr[i]->cpu_idle_exits; cest.cpu_insns = cpu_data_ptr[i]->cpu_cur_insns; cest.cpu_ucc = cpu_data_ptr[i]->cpu_cur_ucc; cest.cpu_urc = cpu_data_ptr[i]->cpu_cur_urc; (void) ml_set_interrupts_enabled(TRUE); copyout(&cest, curpos, sizeof(cest)); curpos += sizeof(cest); } rval = 1; } break; case dgEnaPMC: { boolean_t enable = TRUE; uint32_t cpuinfo[4]; /* Require architectural PMC v2 or higher, corresponding to * Merom+, or equivalent virtualised facility. */ do_cpuid(0xA, &cpuinfo[0]); if ((cpuinfo[0] & 0xFF) >= 2) { mp_cpus_call(CPUMASK_ALL, ASYNC, cpu_pmc_control, &enable); diag_pmc_enabled = TRUE; } rval = 1; } break; #if DEBUG case dgGzallocTest: { (void) ml_set_interrupts_enabled(TRUE); if (diagflag) { unsigned *ptr = (unsigned *)kalloc(1024); kfree(ptr, 1024); *ptr = 0x42; } } break; #endif #if PERMIT_PERMCHECK case dgPermCheck: { (void) ml_set_interrupts_enabled(TRUE); if (diagflag) rval = pmap_permissions_verify(kernel_pmap, kernel_map, 0, ~0ULL); } break; #endif /* PERMIT_PERMCHECK */ default: /* Handle invalid ones */ rval = 0; /* Return an exception */ } regs->rax = rval; return rval; }