static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned sbdn;
int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
sbdn = sysconf.sbdn;
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
device_t dev;
struct resource *res;
uint32_t dword;
dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11,
res->base);
}
/* Initialize interrupt mapping. */
dword = 0x01200000;
pci_write_config32(dev, 0x7c, dword);
dword = 0x12008009;
pci_write_config32(dev, 0x80, dword);
dword = 0x0002010d;
pci_write_config32(dev, 0x84, dword);
}
}
mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0);
// Onboard ck804 smbus
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804,
0xa);
// Onboard ck804 USB 1.1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804,
0x15);
// Onboard ck804 USB 2
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804,
0x14);
// Onboard ck804 SATA 0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804,
0x17);
// Onboard ck804 SATA 1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804,
0x16);
// Onboard ck804 NIC
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 10) << 2) | 0, apicid_ck804,
0x17);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_lintsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_ck804[0], 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_ck804[0], 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums. */
mc->mpe_checksum =
smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int isa_bus;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
printk(BIOS_DEBUG, "%s: apic_id=0x%x\n", __func__, apicid_sb600);
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
{
device_t dev;
dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 0));
if (dev) {
struct resource *res;
res = find_resource(dev, 0x74);
smp_write_ioapic(mc, apicid_sb600, 0x20,
res2mmio(res, 0, 0));
}
}
mptable_add_isa_interrupts(mc, isa_bus, apicid_sb600, 0);
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
/* usb */
PCI_INT(0x0, 0x13, 0x0, 0x10);
PCI_INT(0x0, 0x13, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x2, 0x12);
PCI_INT(0x0, 0x13, 0x3, 0x13);
/* sata */
PCI_INT(0x0, 0x12, 0x1, 0x16);
/* SMBus/ACPI */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* IDE */
PCI_INT(0x0, 0x14, 0x1, 0x11);
/* HDA */
PCI_INT(0x0, 0x14, 0x2, 0x12);
/* LPC */
PCI_INT(0x0, 0x14, 0x3, 0x13);
/* GFX ? */
PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
/* PCIe slots */
PCI_INT(0x2, 0x00, 0x00, 0x10);
PCI_INT(0x2, 0x00, 0x01, 0x11);
PCI_INT(0x2, 0x00, 0x02, 0x12);
PCI_INT(0x2, 0x00, 0x03, 0x13);
/* PCIe slots */
PCI_INT(0x3, 0x00, 0x00, 0x11);
PCI_INT(0x3, 0x00, 0x01, 0x12);
PCI_INT(0x3, 0x00, 0x02, 0x13);
PCI_INT(0x3, 0x00, 0x03, 0x10);
/* PCIe slots */
PCI_INT(0x4, 0x00, 0x00, 0x12);
PCI_INT(0x4, 0x00, 0x01, 0x13);
PCI_INT(0x4, 0x00, 0x02, 0x10);
PCI_INT(0x4, 0x00, 0x03, 0x11);
/* PCIe slots */
PCI_INT(0x5, 0x00, 0x00, 0x13);
PCI_INT(0x5, 0x00, 0x01, 0x10);
PCI_INT(0x5, 0x00, 0x02, 0x11);
PCI_INT(0x5, 0x00, 0x03, 0x12);
/* onboard NIC ? */
PCI_INT(bus_sb600[1], 0x7, 0x0, 0x13);
PCI_INT(bus_sb600[1], 0x7, 0x1, 0x10);
PCI_INT(bus_sb600[1], 0x7, 0x2, 0x11);
PCI_INT(bus_sb600[1], 0x7, 0x3, 0x12);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
mptable_lintsrc(mc, isa_bus);
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
device_t dev;
u32 dword;
u8 byte;
dev =
dev_find_slot(bus_sb600[0],
PCI_DEVFN(sbdn_sb600 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
/* Initialize interrupt mapping */
/* aza */
byte = pci_read_config8(dev, 0x63);
byte &= 0xf8;
byte |= 0; /* 0: INTA, ...., 7: INTH */
pci_write_config8(dev, 0x63, byte);
/* SATA */
dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword);
/*
* 00:12.0: PROG SATA : INT F
* 00:13.0: INTA USB_0
* 00:13.1: INTB USB_1
* 00:13.2: INTC USB_2
* 00:13.3: INTD USB_3
* 00:13.4: INTC USB_4
* 00:13.5: INTD USB2
* 00:14.1: INTA IDE
* 00:14.2: Prog HDA : INT E
* 00:14.5: INTB ACI
* 00:14.6: INTB MCI
*/
}
}
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if CONFIG_GENERATE_ACPI_TABLES == 0
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* usb */
PCI_INT(0x0, 0x13, 0x0, 0x10);
PCI_INT(0x0, 0x13, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x2, 0x12);
PCI_INT(0x0, 0x13, 0x3, 0x13);
/* sata */
PCI_INT(0x0, 0x12, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* on board NIC & Slot PCIE. */
PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
PCI_INT(bus_rs690[2], 0x0, 0x0, 0x12);
PCI_INT(bus_rs690[3], 0x0, 0x0, 0x13);
PCI_INT(bus_rs690[4], 0x0, 0x0, 0x10);
PCI_INT(bus_rs690[5], 0x0, 0x0, 0x11);
PCI_INT(bus_rs690[6], 0x0, 0x0, 0x12);
PCI_INT(bus_rs690[7], 0x0, 0x0, 0x13);
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb600[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb600[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb600[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb600[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb600[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb600[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb600[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb600[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb600[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb600[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned sbdn;
int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
sbdn = sysconf.sbdn;
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
device_t dev;
struct resource *res;
dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11,
res2mmio(res, 0, 0));
}
/* Initialize interrupt mapping. */
/*
LPC bridge PCI config registers:
0x7c:0x0000ffff
- bitmap of masked pci irqs?
- PIRQ[ABCD] possibly?
0x7c:0x00f00000
- sata at f8 - port 1
0x7c:0x0f000000
- sata at f7 - port 1
0x80:0xf0000000
- sata at f7 - port 0
0x80:0x0f000000
- sata at f8 - port 0
0x80:0x0000f000
- EHCI
0x84:0x00000f00
- NIC
0x84:0x0000000f
- OHCI
known values of nibbles:
0 - unrouted?
1 - irq 23
8 - irq 20
c - irq 12
d - irq 21
e - irq 14
f - irq 15
*/
// Enable interrupts for commonly used devices (USB, SATA, etc.)
pci_write_config32(dev, 0x7c, 0x0d800018);
pci_write_config32(dev, 0x80, 0xd8002009);
pci_write_config32(dev, 0x84, 0x00000001);
}
}
mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0);
// Onboard ck804 smbus
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804,
0xa);
// Onboard ck804 USB 1.1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804,
0x15);
// Onboard ck804 USB 2
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804,
0x14);
// Onboard ck804 SATA 0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804,
0x17);
// Onboard ck804 SATA 1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804,
0x16);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
mptable_lintsrc(mc, bus_ck804[0]);
/* There is no extension information... */
/* Compute the checksums. */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned sbdn;
int i, j, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
sbdn = sysconf.sbdn;
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev;
struct resource *res;
uint32_t dword;
dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, apicid_mcp55, 0x11,
res2mmio(res, 0, 0));
}
dword = 0x43c6c643;
pci_write_config32(dev, 0x7c, dword);
dword = 0x81001a00;
pci_write_config32(dev, 0x80, dword);
dword = 0xd00012d2;
pci_write_config32(dev, 0x84, dword);
}
}
mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21
for(j=7; j>=2; j--) {
if(!bus_mcp55[j]) continue;
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
}
}
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04<<2)|i, apicid_mcp55, 0x10 + (0+i)%4);
}
if(bus_pcix[0]) {
for(i=0;i<2;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17
}
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[1], (4<<2)|i, apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17
}
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
mptable_lintsrc(mc, bus_isa);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
struct mb_sysconf_t *m;
unsigned sbdn;
int i, j, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
sbdn = sysconf.sbdn;
m = sysconf.mb;
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
struct device *dev;
struct resource *res;
uint32_t dword;
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, m->apicid_mcp55, 0x11,
res2mmio(res, 0, 0));
}
dword = 0x00000ab5;
pci_write_config32(dev, 0x7c, dword);
dword = 0x5ab0a500;
pci_write_config32(dev, 0x80, dword);
dword = 0xa000000b;
pci_write_config32(dev, 0x84, dword);
}
}
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 1, 1, m->apicid_mcp55, 0x5); /* 5 SMBus, OK */
smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 0, m->apicid_mcp55, 0xb); /* 11 USB, OK */
smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 1, m->apicid_mcp55, 0xa); /* 10 USB, OK */
smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 0, m->apicid_mcp55, 0x5); /* 5 IDE, OK*/
smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 6, 1, m->apicid_mcp55, 0xa); /* 10 VGA, OK*/
smp_write_pci_intsrc(mc, mp_INT, m->bus_8132_2, 3, 0, m->apicid_mcp55, 0x5); /* 5 eth0, OK*/
smp_write_pci_intsrc(mc, mp_INT, m->bus_8132_2, 3, 1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/
for(j = 7;j >= 2; j--) {
if(!m->bus_mcp55[j]) continue;
for(i = 0; i < 4; i++) {
smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[j], 0x00, i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
}
}
for(j = 0; j < 1; j++)
for(i = 0; i < 4; i++) {
smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[1], 0x04+j, i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
mptable_lintsrc(mc, bus_isa);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned sbdn;
int i, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
sbdn = sysconf.sbdn;
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev;
struct resource *res;
uint32_t dword;
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
}
/* Initialize interrupt mapping*/
dword = 0x0120d218;
pci_write_config32(dev, 0x7c, dword);
dword = 0x12008a00;
pci_write_config32(dev, 0x80, dword);
dword = 0x0000007d;
pci_write_config32(dev, 0x84, dword);
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
}
}
}
mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
// Onboard ck804 smbus
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10
// Onboard ck804 USB 1.1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
// Onboard ck804 USB 2
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
// Onboard ck804 SATA 0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
// Onboard ck804 SATA 1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
//Slot PCIE x16
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
}
//Slot PCIE x4
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
}
//Onboard ati
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // 19
//Channel B of 8131
//Onboard Broadcom NIC
for(i=0;i<2;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28
}
//Channel A of 8131
//Slot 4 PCIX 133/100/66
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (0+i)%4); //24
}
//Slot 3 PCIX 133/100/66 SoDIMM PCI
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (2+i)%4); //26
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned sbdn;
int i, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
sbdn = sysconf.sbdn;
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev;
struct resource *res;
uint32_t dword;
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11,
res2mmio(res, 0, 0));
}
/* Initialize interrupt mapping*/
dword = 0x0120d218;
pci_write_config32(dev, 0x7c, dword);
dword = 0x12008a00;
pci_write_config32(dev, 0x80, dword);
dword = 0x0000007d;
pci_write_config32(dev, 0x84, dword);
}
}
mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
// Onboard ck804 smbus
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10
// Onboard ck804 USB 1.1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
// Onboard ck804 USB 2
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
// Onboard ck804 SATA 0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
// Onboard ck804 SATA 1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
//Slot PCIE x16
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
}
//Slot PCIE x4
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
}
//Onboard SM720 VGA
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6<<2)|0, apicid_ck804, 0x13); // 19
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
mptable_lintsrc(mc, bus_isa);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
struct mb_sysconf_t *m;
unsigned sbdn;
int i, j, bus_isa;
unsigned char apicpin[4];
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
sbdn = sysconf.sbdn;
m = sysconf.mb;
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev;
struct resource *res;
uint32_t dword;
dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn+ 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res)
smp_write_ioapic(mc, m->apicid_mcp55, 0x11,
res2mmio(res, 0, 0));
/* Initialize interrupt mapping*/
dword = pci_read_config32(dev, 0x74);
dword &= ~(1<<15);
dword |= 1<<2;
pci_write_config32(dev, 0x74, dword);
dword = 0x43c6c643;
pci_write_config32(dev, 0x7c, dword);
dword = 0x81001a00;
pci_write_config32(dev, 0x80, dword);
dword = 0xd00012d2;
pci_write_config32(dev, 0x84, dword);
}
if (m->bus_mcp55b) {
dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res)
smp_write_ioapic(mc, m->apicid_mcp55b, 0x11,
res2mmio(res, 0, 0));
dword = 0x43c60000;
pci_write_config32(dev, 0x7c, dword);
dword = 0x81000000;
pci_write_config32(dev, 0x80, dword);
dword = 0xd00002d0;
pci_write_config32(dev, 0x84, dword);
}
}
}
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); // 10
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
//Slot PCIE
for (j = 2; j < 8; j++) {
device_t dev;
dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 0x0a + j - 2 , 0));
if (!dev || !dev->enabled)
continue;
for (i = 0; i < 4; i++)
apicpin[i] = 0x10 + (2+j+i+4-sbdn%4)%4;
smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin);
}
//Slot PCI 32
{
device_t dev;
dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 6 , 0));
if (dev && dev->enabled) {
for (i = 0; i < 4; i++)
apicpin[i] = 0x10 + i%4;
smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin);
}
}
if (m->bus_mcp55b) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|0, m->apicid_mcp55b, 0x14); // 20
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|1, m->apicid_mcp55b, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+5)<<2)|2, m->apicid_mcp55b, 0x15); // 21
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+8)<<2)|0, m->apicid_mcp55b, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55b, ((m->sbdnb+9)<<2)|0, m->apicid_mcp55b, 0x15); // 21
//Slot PCIE
for (j = 2; j < 8; j++) {
device_t dev;
dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x0a + j - 2 , 0));
if (!dev || !dev->enabled)
continue;
for (i = 0; i < 4; i++) {
apicpin[i] = 0x10 + (2+j+i+4-m->sbdnb%4)%4;
}
smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55b, apicpin);
}
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
mptable_lintsrc(mc, bus_isa);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
unsigned char bus_pxhd_1;
unsigned char bus_pxhd_2;
unsigned char bus_pxhd_3;
unsigned char bus_pxhd_4;
unsigned char bus_ich5r_1;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
{
device_t dev;
/* ich5r */
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
if (dev) {
bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
bus_ich5r_1 = 7;
}
/* pxhd-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
if (dev) {
bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.0, using defaults\n");
bus_pxhd_1 = 2;
}
/* pxhd-2 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
if (dev) {
bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.2, using defaults\n");
bus_pxhd_2 = 3;
}
/* pxhd-3 */
dev = dev_find_slot(0, PCI_DEVFN(0x4,0));
if (dev) {
bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0, using defaults\n");
bus_pxhd_3 = 5;
}
/* pxhd-4 */
dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
if (dev) {
bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:06.0, using defaults\n");
bus_pxhd_4 = 6;
}
}
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
{
struct resource *res;
device_t dev;
/* pxhd apic 3 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x03, 0x20, res->base);
}
}
else {
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
}
/* pxhd apic 4 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x04, 0x20, res->base);
}
}
else {
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
}
}
mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
/* ISA backward compatibility interrupts */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x74, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x76, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x77, 0x02, 0x17);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x75, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x74, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x7c, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x7d, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_pxhd_1, 0x08, 0x03, 0x00);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_pxhd_1, 0x0c, 0x03, 0x06);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_pxhd_1, 0x0d, 0x03, 0x07);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_pxhd_2, 0x08, 0x04, 0x00);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_ich5r_1, 0x04, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_pxhd_4, 0x00, 0x02, 0x10);
#if 0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
(bus_isa - 1), 0x04, 0x02, 0x10);
#endif
/* Standard local interrupt assignments */
#if 0
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x00, MP_APIC_ALL, 0x00);
#endif
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x00, MP_APIC_ALL, 0x01);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
mptable_lintsrc(mc, bus_isa);
/* There is no extension information... */
/* Compute the checksums. */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
u8 bus_pci = 6;
u8 bus_pcie_a = 1;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
smp_write_ioapic(mc, 0x01, 0x20, IO_APIC_ADDR);
mptable_add_isa_interrupts(mc, bus_isa, 0x1, 0);
/* Standard local interrupt assignments */
mptable_lintsrc(mc, bus_isa);
/* Internal PCI devices */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x01<<2)|0, 0x01, 0x10); /* DMA controller */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x02<<2)|0, 0x01, 0x10); /* PCIe port A */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x03<<2)|0, 0x01, 0x10); /* PCIe port A1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1c<<2)|0, 0x01, 0x10); /* PCIe port B0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1c<<2)|1, 0x01, 0x11); /* PCIe port B1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1c<<2)|2, 0x01, 0x12); /* PCIe port B2 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1c<<2)|3, 0x01, 0x13); /* PCIe port B3 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1d<<2)|0, 0x01, 0x10); /* UHCI0/EHCI */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1d<<2)|1, 0x01, 0x11); /* UHCI1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1e<<2)|0, 0x01, 0x10); /* Audio */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1e<<2)|1, 0x01, 0x11); /* Modem */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1f<<2)|1, 0x01, 0x11); /* SATA/SMBus */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1f<<2)|3, 0x01, 0x13); /* ? */
/* PCI slot */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_pci, 0x00, 0x01, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_pci, 0x01, 0x01, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_pci, 0x02, 0x01, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_pci, 0x03, 0x01, 0x13);
/* PCIe port A slot */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_pcie_a, 0x00, 0x01, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_pcie_a, 0x01, 0x01, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_pcie_a, 0x02, 0x01, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_pcie_a, 0x03, 0x01, 0x13);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int i, j, bus_isa;
struct mb_sysconf_t *m;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
m = sysconf.mb;
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); /* 8111 */
{
device_t dev;
struct resource *res;
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
res2mmio(res, 0, 0));
}
}
j = 0;
for(i = 1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
switch(sysconf.hcid[i]) {
case 1: /* 8132 */
case 3: /* 8131 */
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
res2mmio(res, 0, 0));
}
}
break;
}
j++;
}
}
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
/* ??? What */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
/* Onboard AMD USB */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
/*Slot 3 PCI 32 */
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */
}
/* Slot 4 PCI 32 */
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */
}
/* Slot 1 PCI-X 133/100/66 */
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4);
}
/* Slot 2 PCI-X 133/100/66 */
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); /* 25 */
}
j = 0;
for(i = 1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
int ii;
device_t dev;
struct resource *res;
switch(sysconf.hcid[i]) {
case 1:
case 3:
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
/* Slot 1 PCI-X 133/100/66 */
for(ii = 0; ii < 4; ii++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4);
}
}
}
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
/* Slot 2 PCI-X 133/100/66 */
for(ii = 0; ii < 4; ii++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); /* 25 */
}
}
}
break;
case 2:
/* Slot AGP */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
break;
}
j++;
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
mptable_lintsrc(mc, bus_isa);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
mc = (void*)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, VT8237R_APIC_ID, 0x3, IO_APIC_ADDR);
smp_write_ioapic(mc, K8T890_APIC_ID, 0x3, K8T890_APIC_BASE);
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
/* agp? bridge */
smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 0, VT8237R_APIC_ID, 0x10);
smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 1, VT8237R_APIC_ID, 0x11);
smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 2, VT8237R_APIC_ID, 0x12);
smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 3, VT8237R_APIC_ID, 0x13);
/* peg bridge */
smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);
smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);
smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);
smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);
/* pex bridge */
smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);
smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);
smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);
smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);
/* SATA / IDE */
smp_write_intsrc_pci(mc, 0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x15);
/* USB */
smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x14);
smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x16);
smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 3, VT8237R_APIC_ID, 0x17);
/* PCIE graphics */
smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);
smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);
smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);
smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);
/* onboard PCIE atl1 ethernet */
smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);
smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);
smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);
smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);
/* PCIE slot */
smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);
smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);
smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);
smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);
/* onboard marvell mv6121 sata */
smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);
smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);
smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);
smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);
/* azalia HDCA */
smp_write_intsrc_pci(mc, 6, (0x01 << 2) | 0, VT8237R_APIC_ID, 0x11);
/* pci slot 1 */
smp_write_intsrc_pci(mc, 7, (6 << 2) | 0, VT8237R_APIC_ID, 0x10);
smp_write_intsrc_pci(mc, 7, (6 << 2) | 1, VT8237R_APIC_ID, 0x11);
smp_write_intsrc_pci(mc, 7, (6 << 2) | 2, VT8237R_APIC_ID, 0x12);
smp_write_intsrc_pci(mc, 7, (6 << 2) | 3, VT8237R_APIC_ID, 0x13);
/* pci slot 2 */
smp_write_intsrc_pci(mc, 7, (7 << 2) | 0, VT8237R_APIC_ID, 0x11);
smp_write_intsrc_pci(mc, 7, (7 << 2) | 1, VT8237R_APIC_ID, 0x12);
smp_write_intsrc_pci(mc, 7, (7 << 2) | 2, VT8237R_APIC_ID, 0x13);
smp_write_intsrc_pci(mc, 7, (7 << 2) | 3, VT8237R_APIC_ID, 0x10);
/* pci slot 3 */
smp_write_intsrc_pci(mc, 7, (8 << 2) | 0, VT8237R_APIC_ID, 0x12);
smp_write_intsrc_pci(mc, 7, (8 << 2) | 1, VT8237R_APIC_ID, 0x13);
smp_write_intsrc_pci(mc, 7, (8 << 2) | 2, VT8237R_APIC_ID, 0x10);
smp_write_intsrc_pci(mc, 7, (8 << 2) | 3, VT8237R_APIC_ID, 0x11);
/* pci slot 4 */
smp_write_intsrc_pci(mc, 7, (9 << 2) | 0, VT8237R_APIC_ID, 0x13);
smp_write_intsrc_pci(mc, 7, (9 << 2) | 1, VT8237R_APIC_ID, 0x10);
smp_write_intsrc_pci(mc, 7, (9 << 2) | 2, VT8237R_APIC_ID, 0x11);
smp_write_intsrc_pci(mc, 7, (9 << 2) | 3, VT8237R_APIC_ID, 0x12);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
mptable_lintsrc(mc, 0);
/* There is no extension information... */
/* Compute the checksums. */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
struct mb_sysconf_t *m = sysconf.mb;
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, m->apicid_8131_1, 0x20, res->base);
}
}
dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, m->apicid_8131_2, 0x20, res->base);
}
}
}
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
//
// The commented-out lines are auto-detected on my servers.
//
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
// Integrated SMBus 2.0
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15);
// Integrated AMD AC97 Audio
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11);
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12);
// Integrated AMD USB
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x4 <<2)|0, m->apicid_8111 , 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x0 <<2)|3, m->apicid_8111 , 0x13);
// On board ATI Rage XL
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14);
// On board Broadcom nics
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|0, m->apicid_8131_2, 0x03);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|1, m->apicid_8131_2, 0x00);
// On board LSI SCSI
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02);
// PCIX-133 Slot
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|0, m->apicid_8131_1, 0x01);
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02);
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03);
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
mptable_lintsrc(mc, bus_isa);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int i, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev;
struct resource *res;
uint32_t dword;
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11,
res2mmio(res, 0, 0));
}
/* Initialize interrupt mapping*/
dword = 0x0120d218;
pci_write_config32(dev, 0x7c, dword);
dword = 0x12008a00;
pci_write_config32(dev, 0x80, dword);
dword = 0x00080d7d;
pci_write_config32(dev, 0x84, dword);
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, apicid_8131_1, 0x11,
res2mmio(res, 0, 0));
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, apicid_8131_2, 0x11,
res2mmio(res, 0, 0));
}
}
if(pci1234[2] & 0xf) {
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, apicid_ck804b, 0x11,
res2mmio(res, 0, 0));
}
dword = 0x0000d218;
pci_write_config32(dev, 0x7c, dword);
dword = 0x00000000;
pci_write_config32(dev, 0x80, dword);
dword = 0x00000d00;
pci_write_config32(dev, 0x84, dword);
}
}
}
mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
// Onboard ck804 smbus
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
// 10
// Onboard ck804 USB 1.1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
// Onboard ck804 USB 2
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
// Onboard ck804 Audio
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20
// Onboard ck804 SATA 0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
// Onboard ck804 SATA 1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
// Onboard ck804 NIC
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
//Slot 1 PCIE x16
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00 << 2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
}
//Onboard Firewire
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05 << 2)|0, apicid_ck804, 0x13); // 19
//Slot 2 PCI 32
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04 << 2)|i, apicid_ck804, 0x10 + (0+i)%4);
}
if(pci1234[2] & 0xf) {
//Onboard ck804b NIC
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21 = 53
//Slot 3 PCIE x16
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00 << 2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
}
}
//Channel B of 8131
//Slot 4 PCI-X 100/66
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4 << 2)|i, apicid_8131_2, (0+i)%4);
}
//Slot 5 PCIX 100/66
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9 << 2)|i, apicid_8131_2, (1+i)%4); // 29
}
//OnBoard LSI SCSI
for(i = 0; i < 2; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6 << 2)|i, apicid_8131_2, (2+i)%4); //30
}
//Channel A of 8131
//Slot 6 PCIX 133/100/66
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4 << 2)|i, apicid_8131_1, (0+i)%4); //24
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
mptable_lintsrc(mc, bus_isa);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned sbdn;
int i, j, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
sbdn = sysconf.sbdn;
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev;
struct resource *res;
uint32_t dword;
dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn+ 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, apicid_sis966, 0x11,
res2mmio(res, 0, 0));
}
dword = 0x43c6c643;
pci_write_config32(dev, 0x7c, dword);
dword = 0x81001a00;
pci_write_config32(dev, 0x80, dword);
dword = 0xd0001202;
pci_write_config32(dev, 0x84, dword);
}
}
mptable_add_isa_interrupts(mc, bus_isa, apicid_sis966, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[bus], (((dev)<<2)|(fn)), apicid_sis966, (pin))
PCI_INT(0, sbdn+1, 1, 0xa);
PCI_INT(0, sbdn+2, 0, 0x16); // 22
PCI_INT(0, sbdn+2, 1, 0x17); // 23
PCI_INT(0, sbdn+6, 1, 0x17); // 23
PCI_INT(0, sbdn+5, 0, 0x14); // 20
PCI_INT(0, sbdn+5, 1, 0x17); // 23
PCI_INT(0, sbdn+5, 2, 0x15); // 21
PCI_INT(0, sbdn+8, 0, 0x16); // 22
for(j=7; j>=2; j--) {
if(!bus_sis966[j]) continue;
for(i=0; i<4; i++) {
PCI_INT(j, 0x00, i, 0x10 + (2+j+i+4-sbdn%4)%4);
}
}
for(j=0; j<2; j++)
for(i=0; i<4; i++) {
PCI_INT(1, 0x06+j, i, 0x10 + (2+i+j)%4);
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
mptable_lintsrc(mc, bus_isa);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
struct device *riser = NULL, *firewire = NULL;
int firewire_bus = 0, riser_bus = 0, isa_bus;
int ioapic_id;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
firewire = dev_find_device(0x104c, 0x8023, 0);
if (firewire) {
firewire_bus = firewire->bus->secondary;
}
/* If a riser card is used, this riser is detected on bus 4, so its secondary bus is the */
/* highest bus number on the pci bus. */
riser = dev_find_device(0x3388, 0x0021, 0);
if (!riser)
riser = dev_find_device(0x3388, 0x0022, 0);
if (riser) {
riser_bus = riser->link_list->secondary;
}
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
ioapic_id = 2;
smp_write_ioapic(mc, ioapic_id, 0x20, VIO_APIC_VADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
/* Builtin devices on Bus 0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11);
/* Internal PCI bus (Firewire, PCI slot) */
if (firewire) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x4, ioapic_id, 0x14);
}
if (riser) {
/* Old riser card */
/* riser slot top 5:8.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14);
/* riser slot middle 5:9.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15);
/* riser slot bottom 5:a.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16);
/* New Riser Card */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x30, ioapic_id, 0x14);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x34, ioapic_id, 0x15);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x38, ioapic_id, 0x16);
}
/* PCIe slot */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1, ioapic_id, 0x11);
/* Onboard Ethernet */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
mptable_lintsrc(mc, isa_bus);
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
unsigned sbdn;
get_bus_conf();
sbdn = sysconf.sbdn;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address*/
{
device_t dev;
struct resource *res;
u32 dword;
dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11,
res->base);
}
/* Initialize interrupt mapping */
/* copied from stock bios */
/*0x01800500,0x1800d509,0x00520d08*/
dword = 0x08d0d218;
pci_write_config32(dev, 0x7c, dword);
dword = 0x8d001509;
pci_write_config32(dev, 0x80, dword);
dword = 0x00010271;
pci_write_config32(dev, 0x84, dword);
}
}
/* Now, assemble the table. */
mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0);
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, \
bus_ck804[bus], (((dev)<<2)|(fn)), apicid_ck804, (pin))
#if 0
// Onboard ck804 smbus
PCI_INT(0, sbdn+1, 1, 10); /* (this seems odd, how to test?) */
#endif
// Onboard ck804 USB
PCI_INT(0, sbdn+2, 0, 23);
PCI_INT(0, sbdn+2, 1, 23);
// Onboard ck804 AC-97
PCI_INT(0, sbdn+4, 0, 23);
// Onboard ck804 SATA 0
PCI_INT(0, sbdn+7, 0, 20);
// Onboard ck804 SATA 1
PCI_INT(0, sbdn+8, 0, 21);
// Onboard ck804 NIC
PCI_INT(0, sbdn+10, 0, 22);
/* "AGR" slot */
PCI_INT(1, 0, 0, 16);
PCI_INT(1, 0, 1, 17);
/* legacy PCI */
PCI_INT(1, 7, 0, 17);
PCI_INT(1, 7, 1, 18);
PCI_INT(1, 7, 2, 19);
PCI_INT(1, 7, 3, 16);
PCI_INT(1, 8, 0, 18);
PCI_INT(1, 8, 1, 19);
PCI_INT(1, 8, 2, 16);
PCI_INT(1, 8, 3, 17);
PCI_INT(1, 9, 0, 19);
PCI_INT(1, 9, 1, 16);
PCI_INT(1, 9, 2, 17);
PCI_INT(1, 9, 3, 18);
/* PCI-E x1 port */
PCI_INT(2, 0, 0, 19);
/* XXX guesses */
PCI_INT(2, 0, 1, 16);
PCI_INT(2, 0, 2, 17);
PCI_INT(2, 0, 3, 18);
/* PCI-E x16 port */ /* XXX fix me ? */
PCI_INT(3, 0, 0, 18);
/* XXX guesses */
PCI_INT(3, 0, 1, 19);
PCI_INT(3, 0, 2, 16);
PCI_INT(3, 0, 3, 17);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
mptable_lintsrc(mc, bus_ck804[0]);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
unsigned char bus_8111_0;
unsigned char bus_8111_1;
unsigned char bus_8131_1;
unsigned char bus_8131_2;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
{
device_t dev;
/* 8111 */
dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
if (dev) {
bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
bus_8111_0 = 1;
bus_8111_1 = 4;
}
/* 8131-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
if (dev) {
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
bus_8131_1 = 2;
}
/* 8131-2 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
bus_8131_2 = 3;
}
}
mptable_write_buses(mc, NULL, &bus_isa);
/* Legacy IOAPIC #2 */
smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
/* 8131-1 apic #3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x03, 0x11, res->base);
}
}
/* 8131-2 apic #4 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x04, 0x11, res->base);
}
}
}
mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
/* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
/* Integrated SMBus 2.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|3, 0x2, 0x13);
/* Integrated AMD AC97 Audio */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|1, 0x2, 0x11);
/* Integrated AMD USB */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x00<<2)|3, 0x2, 0x13);
/* On board ATI Rage XL */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, 0x2, 0x10);
/* On board Broadcom nics */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x3, 0x00);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x3, 0x01);
/* On board LSI SCSI */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, 0x3, 0x02);
/* PCI Slot 1 PCIX */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|0, 0x2, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|1, 0x2, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|2, 0x2, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|3, 0x2, 0x13);
/* PCI Slot 2 PCIX */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|0, 0x2, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|1, 0x2, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|2, 0x2, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|3, 0x2, 0x10);
/* Standard local interrupt assignments:
* Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
mptable_lintsrc(mc, bus_isa);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int isa_bus;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x09, 0x20, res->base);
}
}
dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x0a, 0x20, res->base);
}
}
}
mptable_add_isa_interrupts(mc, isa_bus, 0x8, 0);
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
*/
//USB
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7c, 0x8, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x8, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x8, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x8, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x8, 0x17);
//onboard ati
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x8, 0x8, 0x12);
//onboard intel 82551 10/100
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x4, 0x8, 0x11);
// onboard Intel 82547 1000
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x4, 0xa, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x5, 0xa, 0x1);
//Slot 4
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|0, 0x8, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|1, 0x8, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|2, 0x8, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|3, 0x8, 0x11);
//Slot 3
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|0, 0x8, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|1, 0x8, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|2, 0x8, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|3, 0x8, 0x12);
//Slot 1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|0, 0x9, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|1, 0x9, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|2, 0x9, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|3, 0x9, 0x3);
//Slot 2
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|0, 0x9, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|1, 0x9, 0x5);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|2, 0x9, 0x6);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|3, 0x9, 0x7);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
mptable_lintsrc(mc, 0x0);
/*
MP Config Extended Table Entries:
--
System Address Space
bus ID: 0 address type: I/O address
address base: 0x9000
address range: 0x6000
--
System Address Space
bus ID: 0 address type: I/O address
address base: 0x0
address range: 0x100
--
System Address Space
bus ID: 0 address type: memory address
address base: 0xa0000
address range: 0x20000
--
System Address Space
bus ID: 0 address type: memory address
address base: 0xfc700000
address range: 0x2500000
--
System Address Space
bus ID: 0 address type: prefetch address
address base: 0xff600000
address range: 0x500000
--
Bus Heirarchy
bus ID: 5 bus info: 0x01 parent bus ID: 0--
Compatibility Bus Address
bus ID: 0 address modifier: add
predefined range: 0x00000000--
Compatibility Bus Address
bus ID: 0 address modifier: add
predefined range: 0x00000001 // There is no extension information...
*/
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int i, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev = 0;
struct resource *res;
for(i=0; i<3; i++) {
dev = dev_find_device(0x1166, 0x0235, dev);
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, apicid_bcm5785[i],
0x11,
res2mmio(res, 0, 0));
}
}
}
}
mptable_add_isa_interrupts(mc, bus_isa, apicid_bcm5785[0], 0);
//IDE
outb(0x02, 0xc00);
outb(0x0e, 0xc01);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, apicid_bcm5785[0], 0xe); // IDE
//SATA
outb(0x07, 0xc00);
outb(0x0f, 0xc01);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1, (0x0e<<2)|0, apicid_bcm5785[0], 0xf);
//USB
outb(0x01, 0xc00);
outb(0x0a, 0xc01);
for(i=0; i<3; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); //
}
/* enable int */
/* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
{
device_t dev;
dev = dev_find_device(0x1166, 0x0205, 0);
if(dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x6c);
dword |= (1<<4); // enable interrupts
pci_write_config32(dev, 0x6c, dword);
}
}
//First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0
for(i=0; i<4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1_1, (4<<2)|i, apicid_bcm5785[1], 2 + (0+i)%4); //
}
//pci slot (on bcm5785)
for(i=0; i<4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4<<2)|i, apicid_bcm5785[1], i%2); //
}
//onboard ati
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5<<2)|0, apicid_bcm5785[1], 0x1);
//PCI-X on bcm5780
for(i=0; i<4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (4<<2)|i, apicid_bcm5785[1], 6 + (0+i)%4); //
}
for(i=0; i<4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (5<<2)|i, apicid_bcm5785[1], 6 + (1+i)%4); //
}
//onboard Broadcom
for(i=0; i<2; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[2], (4<<2)|i, apicid_bcm5785[1], 0xa + (0+i)%4); //
}
// First PCI-E x8
for(i=0; i<4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[5], (0<<2)|i, apicid_bcm5785[1], 0xe); //
}
// Second PCI-E x8
for(i=0; i<4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0<<2)|i, apicid_bcm5785[1], 0xc); //
}
// Third PCI-E x1
for(i=0; i<4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[4], (0<<2)|i, apicid_bcm5785[1], 0xd); //
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
mptable_lintsrc(mc, bus_isa);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
u32 apicid_sb700;
u32 apicid_rd890;
device_t dev;
u32 dword;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &bus_isa);
/*
* AGESA v5 Apply apic enumeration rules
* For systems with >= 16 APICs, put the IO-APICs at 0..n and
* put the local-APICs at m..z
* For systems with < 16 APICs, put the Local-APICs at 0..n and
* put the IO-APICs at (n + 1)..z
*/
if (CONFIG_MAX_CPUS >= 16)
apicid_sb700 = 0x0;
else
apicid_sb700 = CONFIG_MAX_CPUS + 1;
apicid_rd890 = apicid_sb700 + 1;
//bus_sb700[0], TODO: why bus_sb700[0] use same value of bus_rd890[0] assigned by get_pci1234(), instead of 0.
dev = dev_find_slot(0, PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
/* Set sb700 IOAPIC ID */
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb700, 0x20, dword);
/*
* 00:12.0: PROG SATA : INT F
* 00:13.0: INTA USB_0
* 00:13.1: INTB USB_1
* 00:13.2: INTC USB_2
* 00:13.3: INTD USB_3
* 00:13.4: INTC USB_4
* 00:13.5: INTD USB2
* 00:14.1: INTA IDE
* 00:14.2: Prog HDA : INT E
* 00:14.5: INTB ACI
* 00:14.6: INTB MCI
*/
/* Set RS5650 IOAPIC ID */
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (dev) {
pci_write_config32(dev, 0xF8, 0x1);
dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
smp_write_ioapic(mc, apicid_rd890, 0x20, dword);
}
}
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb700, (pin))
/* SMBUS */
//PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0
/* HD Audio */
PCI_INT(0x0, 0x14, 0x2, 0x10);
/* USB */
/* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */
/* EHCI hard-wired to 02h, corresponding to using INTB# */
/* USB1 */
PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */
PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */
PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */
/* USB2 */
PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */
PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */
PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */
/* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */
PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */
/* SATA */
PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
/* on board NIC & Slot PCIE. */
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rd890[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rd890[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rd890[0x7], 0x0, 0x0, 0x13);
*/
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_rd890, 28); /* dev d */
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_rd890[13], (((0)<<2)|(1)), apicid_rd890, 0); /* card behind dev13 */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
unsigned char bus_pxhd_1;
unsigned char bus_pxhd_2;
unsigned char bus_esb6300_1;
unsigned char bus_esb6300_2;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
{
device_t dev;
/* esb6300_2 */
dev = dev_find_slot(0, PCI_DEVFN(0x1c,0));
if (dev) {
bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1c.0, using defaults\n");
bus_esb6300_1 = 6;
}
/* esb6300_1 */
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
if (dev) {
bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
bus_esb6300_2 = 7;
}
/* pxhd-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
if (dev) {
bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
bus_pxhd_1 = 2;
}
/* pxhd-2 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
if (dev) {
bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
bus_pxhd_2 = 3;
}
}
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000);
{
struct resource *res;
device_t dev;
/* PXHd apic 4 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x04, 0x20, res->base);
}
} else {
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
}
/* PXHd apic 5 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x05, 0x20, res->base);
}
} else {
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
}
}
mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
/* ISA backward compatibility interrupts */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x74, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x77, 0x02, 0x17);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x75, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x7c, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x7d, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
0x03, 0x08, 0x05, 0x00);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
0x03, 0x08, 0x05, 0x04);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
bus_esb6300_1, 0x04, 0x03, 0x00);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
bus_esb6300_1, 0x08, 0x03, 0x01);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
bus_esb6300_2, 0x04, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
bus_esb6300_2, 0x08, 0x02, 0x14);
/* Standard local interrupt assignments */
mptable_lintsrc(mc, bus_isa);
/* FIXME verify I have the irqs handled for all of the risers */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
u32 dword;
u8 byte;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0;
smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if CONFIG_GENERATE_ACPI_TABLES == 0
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x14, 0x4, 0x11);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
unsigned char bus_pxhd_1;
unsigned char bus_pxhd_2;
unsigned char bus_pxhd_3 = 0;
unsigned char bus_pxhd_4 = 0;
unsigned char bus_pxhd_x = 0;
unsigned char bus_ich5r_1;
unsigned int bus_pxhd_id;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
{
device_t dev;
/* ich5r */
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
if (dev) {
bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1f.0, using defaults\n");
bus_ich5r_1 = 4;
}
/* pxhd-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
if (dev) {
bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
bus_pxhd_1 = 2;
}
/* pxhd-2 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
if (dev) {
bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
bus_pxhd_2 = 3;
}
/* test for active riser with 2nd pxh device */
dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
if (dev) {
bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
if(bus_pxhd_id == 0x35998086) {
bus_pxhd_x = pci_read_config8(dev, PCI_SECONDARY_BUS);
/* pxhd-3 */
dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x0,0));
if (dev) {
bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
if(bus_pxhd_id == 0x03298086) {
bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
/* pxhd-4 */
dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,2));
if (dev) {
bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
if(bus_pxhd_id == 0x032a8086) {
bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
}
}
}
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR);
{
struct resource *res;
device_t dev;
/* pxhd apic 3 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x09, 0x20, res->base);
}
}
else {
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
}
/* pxhd apic 4 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x0a, 0x20, res->base);
}
}
else {
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
}
/* pxhd apic 5 */
if(bus_pxhd_3) { /* Active riser pxhd */
dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x0b, 0x20, res->base);
}
}
else {
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.1\n",bus_pxhd_x);
}
}
/* pxhd apic 6 */
if(bus_pxhd_4) { /* active riser pxhd */
dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,3));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x0c, 0x20, res->base);
}
}
else {
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.3\n",bus_pxhd_x);
}
}
}
mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_isa, 0x0a, 0x08, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_isa, 0x0b, 0x08, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_isa, 0x0a, 0x08, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_isa, 0x07, 0x08, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_isa, 0x0b, 0x08, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_isa, 0x05, 0x08, 0x17);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_isa, 0x0b, 0x08, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_isa, 0x07, 0x08, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_isa, 0x0b, 0x08, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_isa, 0x0a, 0x08, 0x10);
/* Standard local interrupt assignments */
mptable_lintsrc(mc, bus_isa);
/* FIXME verify I have the irqs handled for all of the risers */
/* 2:3.0 PCI Slot 1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pxhd_1, (3<<2)|0, 0x9, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pxhd_1, (3<<2)|1, 0x9, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pxhd_1, (3<<2)|2, 0x9, 0x5);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pxhd_1, (3<<2)|3, 0x9, 0x4);
/* 3:7.0 PCI Slot 2 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pxhd_2, (7<<2)|0, 0xa, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pxhd_2, (7<<2)|1, 0xa, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pxhd_2, (7<<2)|2, 0xa, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pxhd_2, (7<<2)|3, 0xa, 0x1);
/* PCI Slot 3 (if active riser) */
if(bus_pxhd_3) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pxhd_3, (1<<2)|0, 0xb, 0x0);
}
/* PCI Slot 4 (if active riser) */
if(bus_pxhd_4) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pxhd_4, (1<<2)|0, 0xc, 0x0);
}
/* Onboard SCSI 0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pxhd_1, (5<<2)|0, 0x9, 0x2);
/* Onboard SCSI 1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pxhd_1, (5<<2)|1, 0x9, 0x1);
/* Onboard NIC 0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pxhd_2, (4<<2)|0, 0xa, 0x6);
/* Onboard NIC 1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pxhd_2, (4<<2)|1, 0xa, 0x7);
/* Onboard VGA */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_ich5r_1, (12<<2)|0, 0x8, 0x11);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
u32 apicid_sp5100;
u32 apicid_sr5650;
device_t dev;
u32 *dword;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &bus_isa);
/*
* AGESA v5 Apply apic enumeration rules
* For systems with >= 16 APICs, put the IO-APICs at 0..n and
* put the local-APICs at m..z
* For systems with < 16 APICs, put the Local-APICs at 0..n and
* put the IO-APICs at (n + 1)..z
*/
if (CONFIG_MAX_CPUS >= 16)
apicid_sp5100 = 0x0;
else
apicid_sp5100 = CONFIG_MAX_CPUS + 1;
apicid_sr5650 = apicid_sp5100 + 1;
dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
if (dev) {
/* Set SP5100 IOAPIC ID */
dword = (u32 *)(uintptr_t)(pci_read_config32(dev, 0x74) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sp5100, 0x20, dword);
#ifdef UNUSED_CODE
u8 byte;
/* Initialize interrupt mapping */
/* aza */
byte = pci_read_config8(dev, 0x63);
byte &= 0xf8;
byte |= 0; /* 0: INTA, ...., 7: INTH */
pci_write_config8(dev, 0x63, byte);
/* SATA */
dword = (u32 *)pci_read_config32(dev, 0xAC);
dword = dword & ~(7 << 26);
dword = dword | (6 << 26); /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */
pci_write_config32(dev, 0xAC, dword);
#endif
/*
* 00:12.0: PROG SATA : INT F
* 00:13.0: INTA USB_0
* 00:13.1: INTB USB_1
* 00:13.2: INTC USB_2
* 00:13.3: INTD USB_3
* 00:13.4: INTC USB_4
* 00:13.5: INTD USB2
* 00:14.1: INTA IDE
* 00:14.2: Prog HDA : INT E
* 00:14.5: INTB ACI
* 00:14.6: INTB MCI
*/
/* Set RS5650 IOAPIC ID */
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (dev) {
pci_write_config32(dev, 0xF8, 0x1);
dword = (u32 *)(uintptr_t)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sr5650, 0x20, dword);
}
}
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sp5100, (pin))
/* SMBUS */
//PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0
/* HD Audio */
PCI_INT(0x0, 0x14, 0x2, 0x10);
/* USB */
/* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */
/* EHCI hard-wired to 02h, corresponding to using INTB# */
/* USB1 */
PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */
PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */
PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */
/* USB2 */
PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */
PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */
PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */
/* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */
PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */
/* SATA */
PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
/* PCI slots */
dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int i, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); //8111
{
device_t dev;
struct resource *res;
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
}
}
}
mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
//??? What
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|3, apicid_8111, 0x13);
//Onboard AMD AC97 Audio
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|1, apicid_8111, 0x11);
// Onboard AMD USB
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
// AGP Display Adapter
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, apicid_8111, 0x10);
//Onboard Serial ATA
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, apicid_8111, 0x11);
//Onboard Firewire
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, apicid_8111, 0x13);
//Onboard Broadcom NIC
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
//Slot 5 PCI 32
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|i, apicid_8111, 0x10 + (0+i)%4); //16
}
//Slot 3 PCIX 100/66
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (3+i)%4); //27
}
//Slot 4 PCIX 100/66
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|i, apicid_8131_1, (2+i)%4); //26
}
//Slot 1 PCI-X 133/100/66
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (0+i)%4); //28
}
//Slot 2 PCI-X 133/100/66
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (1+i)%4); //29
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
mptable_lintsrc(mc, bus_isa);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
device_t dev;
u32 dword;
u8 byte;
dev =
dev_find_slot(bus_sb600[0],
PCI_DEVFN(sbdn_sb600 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb600,
0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
byte = pci_read_config8(dev, 0x63);
byte &= 0xf8;
byte |= 0; /* 0: INTA, ...., 7: INTH */
pci_write_config8(dev, 0x63, byte);
/* SATA */
dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword);
/*
* 00:12.0: PROG SATA : INT F
* 00:13.0: INTA USB_0
* 00:13.1: INTB USB_1
* 00:13.2: INTC USB_2
* 00:13.3: INTD USB_3
* 00:13.4: INTC USB_4
* 00:13.5: INTD USB2
* 00:14.1: INTA IDE
* 00:14.2: Prog HDA : INT E
* 00:14.5: INTB ACI
* 00:14.6: INTB MCI
*/
}
}
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
u32 apicid_sp5100;
u32 apicid_sr5650;
struct device *dev;
uint8_t sp5100_bus_number;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
apicid_sp5100 = 0x0;
else
apicid_sp5100 = 0x20;
apicid_sr5650 = apicid_sp5100 + 1;
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
uint32_t *dword_ptr;
uint32_t dword;
uint16_t word;
uint8_t byte;
sp5100_bus_number = 0; //bus_sp5100[0]; TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0.
dev = dev_find_slot(sp5100_bus_number, PCI_DEVFN(0x14, 0));
if (dev) {
dword_ptr = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sp5100, 0x11, dword_ptr);
/* Initialize interrupt mapping */
/* USB 1 & 2 */
word = pci_read_config16(dev, 0xbe);
word &= ~0x3f3f;
word |= 0x0; /* 0: INTA, ...., 7: INTH */
word |= (0x1 << 3); /* 0: INTA, ...., 7: INTH */
word |= (0x2 << 8); /* 0: INTA, ...., 7: INTH */
word |= (0x3 << 11); /* 0: INTA, ...., 7: INTH */
pci_write_config16(dev, 0xbe, word);
/* USB 3 */
byte = pci_read_config8(dev, 0x63);
byte &= 0xf8;
byte |= (0x2 << 4); /* 0: INTA, ...., 7: INTH */
pci_write_config8(dev, 0x63, byte);
dword = pci_read_config32(dev, 0xac);
/* SATA */
dword &= ~(7 << 26);
dword |= (0x6 << 26); /* 0: INTA, ...., 7: INTH */
/* Hide IDE */
dword &= ~(0x00080000);
/* dword_ptr |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword);
/*
* 00:12.0: PROG SATA : INT F
* 00:13.0: INTA USB_0
* 00:13.1: INTB USB_1
* 00:13.2: INTC USB_2
* 00:13.3: INTD USB_3
* 00:13.4: INTC USB_4
* 00:13.5: INTD USB2
* 00:14.1: INTA IDE
* 00:14.2: Prog HDA : INT E
* 00:14.5: INTB ACI
* 00:14.6: INTB MCI
*/
}
dev = pcidev_on_root(0, 0);
if (dev) {
pci_write_config32(dev, 0xF8, 0x1);
dword_ptr = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sr5650, 0x11, dword_ptr);
}
}
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0);
/* SR5650 devices */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((0)<<2)|(2)), apicid_sr5650, 31); /* Device 0 Function 2 (LNKA, APIC pin 31) */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((2)<<2)|(0)), apicid_sr5650, 28); /* Device 2 (LNKE, APIC pin 28) */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((4)<<2)|(0)), apicid_sr5650, 28); /* Device 4 (LNKF, APIC pin 28) */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((9)<<2)|(0)), apicid_sr5650, 29); /* Device 9 (LNKG, APIC pin 29) */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((10)<<2)|(0)), apicid_sr5650, 30); /* Device 10 (LNKG, APIC pin 30) */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((11)<<2)|(0)), apicid_sr5650, 30); /* Device 11 (LNKG, APIC pin 30) */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* Device 12 (LNKG, APIC pin 30) */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 30); /* Device 13 (LNKG, APIC pin 30)) */
dev = pcidev_on_root(0x2, 0);
if (dev && dev->enabled) {
uint8_t bus_pci = dev->link_list->secondary;
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x2)|(0)), apicid_sr5650, 0); /* card behind dev2 */
}
dev = pcidev_on_root(0x4, 0);
if (dev && dev->enabled) {
uint8_t bus_pci = dev->link_list->secondary;
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x4)|(0)), apicid_sr5650, 0); /* PIKE */
}
dev = pcidev_on_root(0x9, 0);
if (dev && dev->enabled) {
uint8_t bus_pci = dev->link_list->secondary;
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x9)|(0)), apicid_sr5650, 23); /* NIC A */
}
dev = pcidev_on_root(0xa, 0);
if (dev && dev->enabled) {
uint8_t bus_pci = dev->link_list->secondary;
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xa)|(0)), apicid_sr5650, 24); /* NIC B */
}
dev = pcidev_on_root(0xb, 0);
if (dev && dev->enabled) {
uint8_t bus_pci = dev->link_list->secondary;
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xb)|(0)), apicid_sr5650, 0); /* card behind dev11 */
}
dev = pcidev_on_root(0xc, 0);
if (dev && dev->enabled) {
uint8_t bus_pci = dev->link_list->secondary;
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xc)|(0)), apicid_sr5650, 0); /* card behind dev12 */
}
dev = pcidev_on_root(0xd, 0);
if (dev && dev->enabled) {
uint8_t bus_pci = dev->link_list->secondary;
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xd)|(0)), apicid_sr5650, 0); /* card behind dev13 */
}
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, interrupt_signal, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(interrupt_signal)), apicid_sp5100, (pin))
/* USB1 */
PCI_INT(sp5100_bus_number, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */
PCI_INT(sp5100_bus_number, 0x12, 0x1, 0x11); /* OHCI1 Port 3~5 */
/* USB2 */
PCI_INT(sp5100_bus_number, 0x13, 0x0, 0x12); /* OHCI0 Port 6~8 */
PCI_INT(sp5100_bus_number, 0x13, 0x1, 0x13); /* EHCI Port 6~11 */
/* USB3 */
PCI_INT(sp5100_bus_number, 0x14, 0x3, 0x12); /* OHCI0 Port 12~13 */
/* SATA */
PCI_INT(sp5100_bus_number, 0x11, 0x0, 0x16); /* 6, INTG */
/* PCI slots */
dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x1, 0x0, 0x15);
PCI_INT(bus_pci, 0x1, 0x1, 0x16);
PCI_INT(bus_pci, 0x1, 0x2, 0x17);
PCI_INT(bus_pci, 0x1, 0x3, 0x14);
/* PCI_SLOT 1. */
PCI_INT(bus_pci, 0x2, 0x0, 0x14);
PCI_INT(bus_pci, 0x2, 0x1, 0x15);
PCI_INT(bus_pci, 0x2, 0x2, 0x16);
PCI_INT(bus_pci, 0x2, 0x3, 0x17);
/* PCI_SLOT 2. */
PCI_INT(bus_pci, 0x3, 0x0, 0x16);
PCI_INT(bus_pci, 0x3, 0x1, 0x17);
PCI_INT(bus_pci, 0x3, 0x2, 0x14);
PCI_INT(bus_pci, 0x3, 0x3, 0x15);
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
