void mpu_task_on(void *stack) { mpu_disable(); mpu_setaddr(4, (int)(stack + 20)); mpu_setattr(4, mpu_size(CONFIG_TASK_STACK_SIZE) | MPU_RASR_ENABLE | MPU_RASR_ATTR_SCB | MPU_RASR_ATTR_AP_PRW_URW); mpu_enable(); }
void init_m3_state_machine(void) { int i = 0; /* Flush out NVIC interrupts */ for (i=0; i<AM335X_NUM_EXT_INTERRUPTS; i++) { nvic_disable_irq(i); nvic_clear_irq(i); } msg_init(); trace_init(); pm_init(); /* Enable only the MBX IRQ */ nvic_enable_irq(AM335X_IRQ_MBINT0); /* * In the remote case where we disabled the MPU CLOCK * enable it again, no harm in writing to the reg * even if this was not needed */ mpu_enable(); a8_notify(CMD_STAT_PASS); }
void mpu_init(void) { if (!mpu_present()) return; /* User area: prio 0, from start */ mpu_setaddr(0, 0); /* Userspace memory block 0x00000000 (1G) - Internal flash is an exception of this */ mpu_setattr(0, MPUSIZE_1G | MPU_RASR_ENABLE | MPU_RASR_ATTR_SCB | MPU_RASR_ATTR_AP_PRW_URW); mpu_setaddr(1, EXTRAM_START); /* External RAM bank 0x60000000 (512M) */ mpu_setattr(1, MPUSIZE_512M | MPU_RASR_ENABLE | MPU_RASR_ATTR_SCB | MPU_RASR_ATTR_AP_PRW_URW); /* Read-only sectors */ mpu_setaddr(2, FLASH_START); /* Internal Flash 0x00000000 - 0x0FFFFFFF (256M) */ mpu_setattr(2, MPUSIZE_256M | MPU_RASR_ENABLE | MPU_RASR_ATTR_SCB | MPU_RASR_ATTR_AP_PRO_URO); /* System (No user access) */ mpu_setaddr(3, RAM_START); /* Kernel memory 0x20000000 (CONFIG_KRAM_SIZE KB) */ mpu_setattr(3, mpu_size(CONFIG_KRAM_SIZE << 10) | MPU_RASR_ENABLE | MPU_RASR_ATTR_SCB | MPU_RASR_ATTR_AP_PRW_UNO); /* Priority 4 reserved for task stack exception in kernel memory */ mpu_setaddr(5, DEV_START); /* Peripherals 0x40000000 (512MB)*/ mpu_setattr(5, MPUSIZE_1G | MPU_RASR_ENABLE | MPU_RASR_ATTR_S | MPU_RASR_ATTR_B | MPU_RASR_ATTR_AP_PRW_UNO); mpu_setaddr(6, EXTDEV_START); /* External Peripherals 0xA0000000 (1GB) */ mpu_setattr(6, MPUSIZE_1G | MPU_RASR_ENABLE | MPU_RASR_ATTR_S | MPU_RASR_ATTR_B | MPU_RASR_ATTR_AP_PRW_UNO); mpu_setaddr(7, REG_START); /* System Level 0xE0000000 (256MB) */ mpu_setattr(7, MPUSIZE_256M | MPU_RASR_ENABLE | MPU_RASR_ATTR_S | MPU_RASR_ATTR_B | MPU_RASR_ATTR_AP_PRW_UNO); SCB_SHCSR |= SCB_SHCSR_MEMFAULTENA; mpu_enable(); }
void system_disable_jump(void) { disable_jump = 1; #ifdef CONFIG_MPU if (system_is_locked()) { int ret; int enable_mpu = 0; enum system_image_copy_t copy; CPRINTS("MPU type: %08x", mpu_get_type()); /* * Protect RAM from code execution */ ret = mpu_protect_ram(); if (ret == EC_SUCCESS) { enable_mpu = 1; CPRINTS("RAM locked. Exclusion %08x-%08x", &__iram_text_start, &__iram_text_end); } else { CPRINTS("Failed to lock RAM (%d)", ret); } /* * Protect inactive image (ie. RO if running RW, vice versa) * from code execution. */ switch (system_get_image_copy()) { case SYSTEM_IMAGE_RO: ret = mpu_lock_rw_flash(); copy = SYSTEM_IMAGE_RW; break; case SYSTEM_IMAGE_RW: ret = mpu_lock_ro_flash(); copy = SYSTEM_IMAGE_RO; break; default: copy = SYSTEM_IMAGE_UNKNOWN; ret = !EC_SUCCESS; } if (ret == EC_SUCCESS) { enable_mpu = 1; CPRINTS("%s image locked", system_image_copy_t_to_string(copy)); } else { CPRINTS("Failed to lock %s image (%d)", system_image_copy_t_to_string(copy), ret); } if (enable_mpu) mpu_enable(); } else { CPRINTS("System is unlocked. Skip MPU configuration"); } #endif }
static int mpu_resume(struct device *dev) { struct mpu_data *mpu = dev_get_drvdata(dev); enable_irq(mpu->client->irq); mutex_lock(&mpu->lock); if (mpu->enabled) mpu_enable(mpu); mutex_unlock(&mpu->lock); return 0; }
int main(void) { irq_init(); irq_disable(); #ifdef CONFIG_FPU *SCB_CPACR |= (SCB_CPACR_CP10_FULL | SCB_CPACR_CP11_FULL); #endif #ifdef CONFIG_DEBUG dbg_device_init(); dbg_layer = DL_KDB; #endif __l4_printf("%s", banner); run_init_hook(INIT_LEVEL_PLATFORM); #ifdef CONFIG_SYMMAP ksym_init(); #endif sched_init(); memory_init(); syscall_init(); thread_init_subsys(); ktimer_event_init(); #ifdef CONFIG_KPROBES kprobe_init(); #endif /* CONFIG_KPROBES */ #ifdef CONFIG_KDB softirq_register(KDB_SOFTIRQ, debug_kdb_handler); dbg_puts("Press '?' to print KDB menu\n"); #endif run_init_hook(INIT_LEVEL_KERNEL); /* Not creating kernel thread here because it corrupts current stack */ create_idle_thread(); create_root_thread(); ktimer_event_create(64, ipc_deliver, NULL); mpu_enable(MPU_ENABLED); run_init_hook(INIT_LEVEL_LAST); switch_to_kernel(); /* Not reached */ return 0; }
/*---------------------------------------------------------------*/ PROCESS_THREAD(null_app_process, ev, data) { PROCESS_BEGIN(); printf("MPU6050 ACC Started\n"); #ifdef SF_FEATURE_SHELL_OPT serial_shell_init(); remote_shell_init(); shell_reboot_init(); shell_blink_init(); shell_sky_init(); #endif static uint8_t MPU_status2 = 0; uint8_t i; app_conn_open(&nullApp_callback); if (node_id != 0) { MPU_status2 = 0; for(i = 0; i < 100 &(~MPU_status2);i++) { MPU_status2 = mpu_enable(); } if(MPU_status2 == 0) { printf("MPU could not be enabled\n"); } MPU_status2 = 0; for(i = 0; i < 100 &(~MPU_status2);i++) { MPU_status2 = mpu_wakeup(); } if(MPU_status2 == 0) { printf("MPU could not be awakened\n"); } ctimer_set(&ct,SAMPLE_RATE,sample_fun,(void*)NULL); } PROCESS_END(); }
static ssize_t attr_set_enable(struct device *dev, struct device_attribute *attr, const char *buf, size_t size) { struct mpu_data *mpu = dev_get_drvdata(dev); unsigned long val; if (strict_strtoul(buf, 10, &val)) return -EINVAL; dev_dbg(dev, "gyro set enable %ld\n", val); mutex_lock(&mpu->lock); if (val) mpu_enable(mpu); else mpu_disable(mpu); mpu->enabled = val; mutex_unlock(&mpu->lock); return size; }
/*---------------------------------------------------------------*/ PROCESS_THREAD(null_app_process, ev, data) { PROCESS_BEGIN(); printf("Sensor No Comm Started\n"); // turn off radio NETSTACK_RDC.off(0); NETSTACK_RADIO.off(); // connect with MPU static uint8_t MPU_status = 0; static mpu_data_union samples; static struct etimer rxtimer; int i = 0; if (node_id != 0) { MPU_status = 0; for(i = 0; i < 100 & (~MPU_status);i++) { MPU_status = mpu_enable(); } if (MPU_status == 0) printf("MPU could not be enabled.\n"); MPU_status = 0; for(i = 0; i < 100 & (~MPU_status);i++) { MPU_status = mpu_wakeup(); } if (MPU_status == 0) { printf("MPU could not be awakened.\n"); } etimer_set(&rxtimer, (unsigned long)(CLOCK_SECOND/SAMPLING_FREQ)); } // sampling if (node_id != 0) { while(1) { PROCESS_WAIT_EVENT_UNTIL(etimer_expired(&rxtimer)); etimer_reset(&rxtimer); MPU_status = mpu_sample_all(&samples); if (MPU_status != 0) { printf("%d,%d,%d,%d\n",samples.data.accel_x,samples.data.accel_y,samples.data.accel_z,samples.data.temperature); } else { printf("Cannot sample data\n"); } } } PROCESS_END(); }
/*---------------------------------------------------------------*/ PROCESS_THREAD(null_app_process, ev, data) { static struct etimer rxtimer; PROCESS_BEGIN(); app_conn_open(&nullApp_callback); uint8_t i; uint8_t temp; static uint8_t MPU_status = 0; static mpu_data_acc_gyro_union samples; if (node_id != 0) { MPU_status = 0; for(i = 0; i < 100 & (~MPU_status);i++) { MPU_status = mpu_enable(); } if (MPU_status == 0) printf("MPU could not be enabled.\n"); MPU_status = 0; for(i = 0; i < 100 & (~MPU_status);i++) { MPU_status = mpu_wakeup(); } if (MPU_status == 0) { printf("MPU could not be awakened.\n"); } etimer_set(&rxtimer, (unsigned long)(CLOCK_SECOND/SAMPLING_FREQ)); } else { etimer_set(&rxtimer,CLOCK_SECOND/20); } if (node_id != 0) { while(1) { //MPU_PRINT_BYTE(54); PROCESS_WAIT_EVENT_UNTIL(etimer_expired(&rxtimer)); etimer_reset(&rxtimer); //MPU_PRINT_BYTE(55); MPU_status = mpu_sample_acc(&samples); if (MPU_status != 0) { //printf("%u,%u,%u\n",samples.data.x,samples.data.y,samples.data.z); //print_mpu_sample_acc_gyro(&samples); // MPU_PRINT_BYTE(samples.reg.x_h); // MPU_PRINT_BYTE(samples.reg.x_l); // MPU_PRINT_BYTE(samples.reg.y_h); // MPU_PRINT_BYTE(samples.reg.y_l); // MPU_PRINT_BYTE('\n'); // read_mpu_reg(MPU6050_RA_INT_STATUS,&temp); // printf("%u",temp); app_conn_send((uint8_t *)(&samples),MPU_DATA_ACC_GYRO_SIZE); } else printf("Cannot sample data\n"); } } PROCESS_END(); }
/*---------------------------------------------------------------*/ PROCESS_THREAD(null_app_process, ev, data) { static struct etimer rxtimer; PROCESS_BEGIN(); printf("Hello world Started.\n"); #ifdef SF_FEATURE_SHELL_OPT serial_shell_init(); remote_shell_init(); shell_reboot_init(); shell_blink_init(); shell_sky_init(); #endif app_conn_open(&nullApp_callback); #ifdef ADC_SENSOR static uint16_t samples[ADC_SAMPLES_PER_FRAME]={0}; uint8_t i; // static uint8_t samples_sorted_bytes[2*ADC_SAMPLES_PER_FRAME]; static uint8_t sample_num = 0; //increments from 0 to samples_per_frame-1 if (node_id != 0){ adc_on(); //adc_configure(0); //to sample reference voltage (Vref/2), ~2048. etimer_set( &rxtimer, (unsigned long)(CLOCK_SECOND/(ADC_SAMPLING_FREQ))); } else etimer_set(&rxtimer,CLOCK_SECOND/20); if(node_id != 0) { while(1) { PROCESS_WAIT_EVENT_UNTIL(etimer_expired(&rxtimer)); etimer_reset(&rxtimer); samples[sample_num]=adc_sample(); sample_num++; if(sample_num == ADC_SAMPLES_PER_FRAME){ sample_num=0; /* * Byte order needs to be reversed because of low-endian system. * Can be done at AP level too, if needed. */ // for(i=0;i<ADC_SAMPLES_PER_FRAME;i++){ // samples_sorted_bytes[2*i]=(samples[i]>>8); // samples_sorted_bytes[2*i+1]= (samples[i]& 0xff); // } //app_conn_send(samples_sorted_bytes,sizeof(uint8_t)*ADC_SAMPLES_PER_FRAME*2); tdma_rdc_buf_ptr = 0; tdma_rdc_buf_send_ptr = 0; tdma_rdc_buf_full_flg = 0; app_conn_send(samples,sizeof(uint16_t)*ADC_SAMPLES_PER_FRAME/sizeof(uint8_t)); } } } #endif #ifdef I2C_SENSOR //static rtimer_clock_t rt, del; int i; static uint8_t MPU_status = 0; static uint8_t sample_count = 0; /* static uint8_t samples_sorted_bytes[14*MPU_SAMPLES_PER_FRAME],comp_samples_sorted_bytes[14*MPU_SAMPLES_PER_FRAME]; static uint8_t sample_num=0, uncomp_data_len=14*MPU_SAMPLES_PER_FRAME,comp_data_len; static uint8_t *st; */ static mpu_data sampleArray[MPU_SAMPLES_PER_FRAME]; if (node_id != 0){ MPU_status = 0; for(i = 0; i < 100 & (~MPU_status);i++) { MPU_status = mpu_enable(); } if (MPU_status == 0) printf("MPU could not be enabled.\n"); MPU_status = 0; for(i = 0; i < 100 & (~MPU_status);i++) { MPU_status = mpu_wakeup(); } if (MPU_status == 0) printf("MPU could not be awakened.\n"); etimer_set(&rxtimer, (unsigned long)(CLOCK_SECOND/MPU_SAMPLING_FREQ)); } else etimer_set(&rxtimer,CLOCK_SECOND/20); if(node_id != 0) { while(1){ PROCESS_WAIT_EVENT_UNTIL(etimer_expired(&rxtimer)); etimer_reset(&rxtimer); mpu_data_union samples; int m=mpu_sample_all(&samples); app_conn_send((uint8_t *)(&samples),MPU_DATA_SIZE); /* sampleArray[sample_count] = samples.data; sample_count = sample_count + 1; if(sample_count == MPU_SAMPLES_PER_FRAME) { sample_count = 0; tdma_rdc_buf_clear(); app_conn_send(sampleArray,MPU_DATA_SIZE*MPU_SAMPLES_PER_FRAME); } */ /* st = &samples; for(i=0;i<7;i++){ samples_sorted_bytes[2*i+14*sample_num]=*(st+2*i+1); samples_sorted_bytes[2*i+1+14*sample_num]= *(st+2*i); } sample_num++; if(sample_num==MPU_SAMPLES_PER_FRAME){ sample_num=0; app_conn_send(samples_sorted_bytes,sizeof(uint8_t)*14*MPU_SAMPLES_PER_FRAME); } PRINTF("%d,%d,%d,%d,%d,%d,%d\n",samples.data.accel_x,samples.data.accel_y,samples.data.accel_z,samples.data.gyro_x,samples.data.gyro_y, samples.data.gyro_z,samples.data.temperature); */ // app_conn_send(&samples,sizeof(mpu_data)/sizeof(uint8_t)); } } #endif PROCESS_END(); }
/*---------------------------------------------------------------*/ PROCESS_THREAD(null_app_process, ev, data) { PROCESS_BEGIN(); printf("MPU6050 Started\n"); #ifdef SF_FEATURE_SHELL_OPT serial_shell_init(); remote_shell_init(); shell_reboot_init(); shell_blink_init(); shell_sky_init(); #endif uint8_t i; app_conn_open(&nullApp_callback); if (node_id > 0) { MPU_status = 0; for(i = 0; i < 100 &(~MPU_status);i++) { MPU_status = mpu_enable(); } if(MPU_status == 0) { printf("MPU could not be enabled\n"); } MPU_status = 0; for(i = 0; i < 100 &(~MPU_status);i++) { MPU_status = mpu_wakeup(); } if(MPU_status == 0) { printf("MPU could not be awakened\n"); } /* configurate MPU6050 sensor */ uint8_t MPU_config = 0; // disable sleep model read_mpu_reg(MPU_RA_PWR_MGMT1,&MPU_config); MPU_config = MPU_config & ~BV(6); // set bit 6 to 0 write_mpu_reg(MPU_RA_PWR_MGMT1,MPU_config); #if DEBUG read_mpu_reg(MPU_RA_PWR_MGMT1,&MPU_config); PRINTF("power management 1: %u\n",MPU_config); #endif // disable cycle read_mpu_reg(MPU_RA_PWR_MGMT1,&MPU_config); MPU_config = MPU_config & ~BV(5); // set bit 5 to 0 write_mpu_reg(MPU_RA_PWR_MGMT1,MPU_config); #if DEBUG read_mpu_reg(MPU_RA_PWR_MGMT1,&MPU_config); PRINTF("power management 1: %u\n",MPU_config); #endif // gyro range: -/+ 250 degree/sec read_mpu_reg(MPU_GYRO_CONFIG,&MPU_config); MPU_config = MPU_config & ~BV(3); // set bit 3 to zero write_mpu_reg(MPU_GYRO_CONFIG,MPU_config); #if DEBUG read_mpu_reg(MPU_GYRO_CONFIG,&MPU_config); PRINTF("Gyro config: %u\n",MPU_config); #endif // accelerometer range: -/+ 2g read_mpu_reg(MPU_ACCEL_CONFIG,&MPU_config); MPU_config = MPU_config & ~BV(3); // set bit 3 to zero -/+ 2g //MPU_config = MPU_config | BV(4); // set bit 4 to one -/+ 8g write_mpu_reg(MPU_ACCEL_CONFIG,MPU_config); read_mpu_reg(MPU_ACCEL_CONFIG,&MPU_config); printf("Acceleromter config: %u\n",MPU_config); // LPF: cut-off 21Hz for accel and 20Hz for gyro; DLPF_CFG = 4 read_mpu_reg(MPU_CONFIG,&MPU_config); MPU_config = MPU_config | BV(2); // set bit 2 to 1, DLPF_CFG = 4 write_mpu_reg(MPU_CONFIG,MPU_config); #if DEBUG read_mpu_reg(MPU_CONFIG,&MPU_config); PRINTF("MPU 6050 config: %u\n",MPU_config); #endif // sampling rate 1kHz write_mpu_reg(MPU_SMPLRT_DIV,0); #if DEBUG read_mpu_reg(MPU_SMPLRT_DIV,&MPU_config); PRINTF("sample divider: %u\n",MPU_config); #endif // start sampling ctimer_set(&ct,SAMPLE_RATE,sample_fun,(void*)NULL); ctimer_set(&reset_timer,SAMPLE_RATE*50,reset_sample_timer,(void*)NULL); } else { print_MPU = 1; } PROCESS_END(); }
/** * \brief Set up a memory region. */ static void _setup_memory_region( void ) { uint32_t dw_region_base_addr; uint32_t dw_region_attr; __DMB(); /** * ITCM memory region --- Normal * START_Addr:- 0x00000000UL * END_Addr:- 0x00400000UL */ dw_region_base_addr = ITCM_START_ADDRESS | MPU_REGION_VALID | MPU_DEFAULT_ITCM_REGION; dw_region_attr = MPU_AP_PRIVILEGED_READ_WRITE | mpu_cal_mpu_region_size(ITCM_END_ADDRESS - ITCM_START_ADDRESS) | MPU_REGION_ENABLE; mpu_set_region( dw_region_base_addr, dw_region_attr); /** * Internal flash memory region --- Normal read-only * (update to Strongly ordered in write accesses) * START_Addr:- 0x00400000UL * END_Addr:- 0x00600000UL */ dw_region_base_addr = IFLASH_START_ADDRESS | MPU_REGION_VALID | MPU_DEFAULT_IFLASH_REGION; dw_region_attr = MPU_AP_READONLY | INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) | mpu_cal_mpu_region_size(IFLASH_END_ADDRESS - IFLASH_START_ADDRESS) | MPU_REGION_ENABLE; mpu_set_region( dw_region_base_addr, dw_region_attr); /** * DTCM memory region --- Normal * START_Addr:- 0x20000000L * END_Addr:- 0x20400000UL */ /* DTCM memory region */ dw_region_base_addr = DTCM_START_ADDRESS | MPU_REGION_VALID | MPU_DEFAULT_DTCM_REGION; dw_region_attr = MPU_AP_PRIVILEGED_READ_WRITE | mpu_cal_mpu_region_size(DTCM_END_ADDRESS - DTCM_START_ADDRESS) | MPU_REGION_ENABLE; mpu_set_region( dw_region_base_addr, dw_region_attr); /** * SRAM Cacheable memory region --- Normal * START_Addr:- 0x20400000UL * END_Addr:- 0x2043FFFFUL */ /* SRAM memory region */ dw_region_base_addr = SRAM_FIRST_START_ADDRESS | MPU_REGION_VALID | MPU_DEFAULT_SRAM_REGION_1; dw_region_attr = MPU_AP_FULL_ACCESS | INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) | mpu_cal_mpu_region_size(SRAM_FIRST_END_ADDRESS - SRAM_FIRST_START_ADDRESS) | MPU_REGION_ENABLE; mpu_set_region( dw_region_base_addr, dw_region_attr); /** * Internal SRAM second partition memory region --- Normal * START_Addr:- 0x20440000UL * END_Addr:- 0x2045FFFFUL */ /* SRAM memory region */ dw_region_base_addr = SRAM_SECOND_START_ADDRESS | MPU_REGION_VALID | MPU_DEFAULT_SRAM_REGION_2; dw_region_attr = MPU_AP_FULL_ACCESS | INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) | mpu_cal_mpu_region_size(SRAM_SECOND_END_ADDRESS - SRAM_SECOND_START_ADDRESS) | MPU_REGION_ENABLE; mpu_set_region( dw_region_base_addr, dw_region_attr); #ifdef MPU_HAS_NOCACHE_REGION dw_region_base_addr = SRAM_NOCACHE_START_ADDRESS | MPU_REGION_VALID | MPU_NOCACHE_SRAM_REGION; dw_region_attr = MPU_AP_FULL_ACCESS | INNER_OUTER_NORMAL_NOCACHE_TYPE( SHAREABLE ) | mpu_cal_mpu_region_size(NOCACHE_SRAM_REGION_SIZE) | MPU_REGION_ENABLE; mpu_set_region( dw_region_base_addr, dw_region_attr); #endif /** * Peripheral memory region --- DEVICE Shareable * START_Addr:- 0x40000000UL * END_Addr:- 0x5FFFFFFFUL */ dw_region_base_addr = PERIPHERALS_START_ADDRESS | MPU_REGION_VALID | MPU_PERIPHERALS_REGION; dw_region_attr = MPU_AP_FULL_ACCESS | MPU_REGION_EXECUTE_NEVER | SHAREABLE_DEVICE_TYPE | mpu_cal_mpu_region_size(PERIPHERALS_END_ADDRESS - PERIPHERALS_START_ADDRESS) |MPU_REGION_ENABLE; mpu_set_region( dw_region_base_addr, dw_region_attr); /** * External EBI memory memory region --- Strongly Ordered * START_Addr:- 0x60000000UL * END_Addr:- 0x6FFFFFFFUL */ dw_region_base_addr = EXT_EBI_START_ADDRESS | MPU_REGION_VALID | MPU_EXT_EBI_REGION; dw_region_attr = MPU_AP_FULL_ACCESS | /* External memory Must be defined with 'Device' or 'Strongly Ordered' attribute for write accesses (AXI) */ STRONGLY_ORDERED_SHAREABLE_TYPE | mpu_cal_mpu_region_size(EXT_EBI_END_ADDRESS - EXT_EBI_START_ADDRESS) | MPU_REGION_ENABLE; mpu_set_region( dw_region_base_addr, dw_region_attr); /** * SDRAM cacheable memory region --- Normal * START_Addr:- 0x70000000UL * END_Addr:- 0x7FFFFFFFUL */ dw_region_base_addr = SDRAM_START_ADDRESS | MPU_REGION_VALID | MPU_DEFAULT_SDRAM_REGION; dw_region_attr = MPU_AP_FULL_ACCESS | INNER_NORMAL_WB_RWA_TYPE( SHAREABLE ) | mpu_cal_mpu_region_size(SDRAM_END_ADDRESS - SDRAM_START_ADDRESS) | MPU_REGION_ENABLE; mpu_set_region( dw_region_base_addr, dw_region_attr); /** * QSPI memory region --- Strongly ordered * START_Addr:- 0x80000000UL * END_Addr:- 0x9FFFFFFFUL */ dw_region_base_addr = QSPI_START_ADDRESS | MPU_REGION_VALID | MPU_QSPIMEM_REGION; dw_region_attr = MPU_AP_FULL_ACCESS | STRONGLY_ORDERED_SHAREABLE_TYPE | mpu_cal_mpu_region_size(QSPI_END_ADDRESS - QSPI_START_ADDRESS) | MPU_REGION_ENABLE; mpu_set_region( dw_region_base_addr, dw_region_attr); /** * USB RAM Memory region --- Device * START_Addr:- 0xA0100000UL * END_Addr:- 0xA01FFFFFUL */ dw_region_base_addr = USBHSRAM_START_ADDRESS | MPU_REGION_VALID | MPU_USBHSRAM_REGION; dw_region_attr = MPU_AP_FULL_ACCESS | MPU_REGION_EXECUTE_NEVER | SHAREABLE_DEVICE_TYPE | mpu_cal_mpu_region_size(USBHSRAM_END_ADDRESS - USBHSRAM_START_ADDRESS) | MPU_REGION_ENABLE; mpu_set_region( dw_region_base_addr, dw_region_attr); /* Enable the memory management fault , Bus Fault, Usage Fault exception */ SCB->SHCSR |= (SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_USGFAULTENA_Msk); /* Enable the MPU region */ mpu_enable( MPU_ENABLE | MPU_PRIVDEFENA); __DSB(); __ISB(); }