static int printlock_w39_bootblock_64k16k(uint8_t lock)
{
msg_cdbg("Software 64 kB bootblock locking is %sactive.\n",
(lock & (1 << 0)) ? "" : "not ");
msg_cdbg("Software 16 kB bootblock locking is %sactive.\n",
(lock & (1 << 1)) ? "" : "not ");
if (lock & ((1 << 1) | (1 << 0)))
return -1;
return 0;
}
static int printlock_w39_tblwp(uint8_t lock)
{
msg_cdbg("Hardware bootblock locking (#TBL) is %sactive.\n",
(lock & (1 << 2)) ? "" : "not ");
msg_cdbg("Hardware remaining chip locking (#WP) is %sactive..\n",
(lock & (1 << 3)) ? "" : "not ");
if (lock & ((1 << 2) | (1 << 3)))
return -1;
return 0;
}
int printlock_w39l040(struct flashchip * flash)
{
uint8_t lock;
int ret;
lock = w39_idmode_readb(flash, 0x00002);
msg_cdbg("Bottom boot block:\n");
ret = printlock_w39_bootblock_64k16k(lock);
lock = w39_idmode_readb(flash, 0x7fff2);
msg_cdbg("Top boot block:\n");
ret |= printlock_w39_bootblock_64k16k(lock);
return ret;
}
int printlock_w39f010(struct flashctx *flash)
{
uint8_t lock;
int ret;
lock = w39_idmode_readb(flash, 0x00002);
msg_cdbg("Bottom boot block:\n");
ret = printlock_w39_single_bootblock(lock, 16);
lock = w39_idmode_readb(flash, 0x1fff2);
msg_cdbg("Top boot block:\n");
ret |= printlock_w39_single_bootblock(lock, 16);
return ret;
}
int probe_82802ab(struct flashctx *flash)
{
chipaddr bios = flash->virtual_memory;
uint8_t id1, id2, flashcontent1, flashcontent2;
int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0;
/* Reset to get a clean state */
chip_writeb(flash, 0xFF, bios);
programmer_delay(10);
/* Enter ID mode */
chip_writeb(flash, 0x90, bios);
programmer_delay(10);
id1 = chip_readb(flash, bios + (0x00 << shifted));
id2 = chip_readb(flash, bios + (0x01 << shifted));
/* Leave ID mode */
chip_writeb(flash, 0xFF, bios);
programmer_delay(10);
msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2);
if (!oddparity(id1))
msg_cdbg(", id1 parity violation");
/*
* Read the product ID location again. We should now see normal
* flash contents.
*/
flashcontent1 = chip_readb(flash, bios + (0x00 << shifted));
flashcontent2 = chip_readb(flash, bios + (0x01 << shifted));
if (id1 == flashcontent1)
msg_cdbg(", id1 is normal flash content");
if (id2 == flashcontent2)
msg_cdbg(", id2 is normal flash content");
msg_cdbg("\n");
if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id)
return 0;
if (flash->chip->feature_bits & FEATURE_REGISTERMAP)
map_flash_registers(flash);
return 1;
}
int probe_m29f400bt(struct flashctx *flash)
{
chipaddr bios = flash->virtual_memory;
uint8_t id1, id2;
chip_writeb(flash, 0xAA, bios + 0xAAA);
chip_writeb(flash, 0x55, bios + 0x555);
chip_writeb(flash, 0x90, bios + 0xAAA);
programmer_delay(10);
id1 = chip_readb(flash, bios);
/* The data sheet says id2 is at (bios + 0x01) and id2 listed in
* flash.h does not match. It should be possible to use JEDEC probe.
*/
id2 = chip_readb(flash, bios + 0x02);
chip_writeb(flash, 0xAA, bios + 0xAAA);
chip_writeb(flash, 0x55, bios + 0x555);
chip_writeb(flash, 0xF0, bios + 0xAAA);
programmer_delay(10);
msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
if (id1 == flash->chip->manufacture_id && id2 == flash->chip->model_id)
return 1;
return 0;
}
int printlock_at49f(struct flashctx *flash)
{
uint8_t lock = w39_idmode_readb(flash, 0x00002);
msg_cdbg("Hardware bootblock lockout is %sactive.\n",
(lock & 0x01) ? "" : "not ");
return 0;
}
/* According to the Winbond W29EE011, W29EE012, W29C010M, W29C011A
* datasheets this is the only valid probe function for those chips.
*/
int probe_w29ee011(struct flashctx *flash)
{
chipaddr bios = flash->virtual_memory;
uint8_t id1, id2;
if (!chip_to_probe || strcmp(chip_to_probe, flash->chip->name)) {
msg_cdbg("Old Winbond W29* probe method disabled because "
"the probing sequence puts the AMIC A49LF040A in "
"a funky state. Use 'flashrom -c %s' if you "
"have a board with such a chip.\n", flash->chip->name);
return 0;
}
/* Issue JEDEC Product ID Entry command */
chip_writeb(flash, 0xAA, bios + 0x5555);
programmer_delay(10);
chip_writeb(flash, 0x55, bios + 0x2AAA);
programmer_delay(10);
chip_writeb(flash, 0x80, bios + 0x5555);
programmer_delay(10);
chip_writeb(flash, 0xAA, bios + 0x5555);
programmer_delay(10);
chip_writeb(flash, 0x55, bios + 0x2AAA);
programmer_delay(10);
chip_writeb(flash, 0x60, bios + 0x5555);
programmer_delay(10);
/* Read product ID */
id1 = chip_readb(flash, bios);
id2 = chip_readb(flash, bios + 0x01);
/* Issue JEDEC Product ID Exit command */
chip_writeb(flash, 0xAA, bios + 0x5555);
programmer_delay(10);
chip_writeb(flash, 0x55, bios + 0x2AAA);
programmer_delay(10);
chip_writeb(flash, 0xF0, bios + 0x5555);
programmer_delay(10);
msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
if (id1 == flash->chip->manufacture_id && id2 == flash->chip->model_id)
return 1;
return 0;
}
static int printlock_w39_common(struct flashchip *flash, int offset)
{
uint8_t lock;
lock = w39_idmode_readb(flash, offset);
msg_cdbg("Lockout bits:\n");
return printlock_w39_tblwp(lock);
}
static int printlock_w39_single_bootblock(uint8_t lock, uint16_t kB)
{
msg_cdbg("Software %d kB bootblock locking is %sactive.\n", kB, (lock & 0x03) ? "" : "not ");
if (lock & 0x03)
return -1;
return 0;
}
void print_status_82802ab(uint8_t status)
{
msg_cdbg("%s", status & 0x80 ? "Ready:" : "Busy:");
msg_cdbg("%s", status & 0x40 ? "BE SUSPEND:" : "BE RUN/FINISH:");
msg_cdbg("%s", status & 0x20 ? "BE ERROR:" : "BE OK:");
msg_cdbg("%s", status & 0x10 ? "PROG ERR:" : "PROG OK:");
msg_cdbg("%s", status & 0x8 ? "VP ERR:" : "VPP OK:");
msg_cdbg("%s", status & 0x4 ? "PROG SUSPEND:" : "PROG RUN/FINISH:");
msg_cdbg("%s", status & 0x2 ? "WP|TBL#|WP#,ABORT:" : "UNLOCK:");
}
int unlock_lh28f008bjt(struct flashctx *flash)
{
chipaddr bios = flash->virtual_memory;
uint8_t mcfg, bcfg;
uint8_t need_unlock = 0, can_unlock = 0;
int i;
/* Wait if chip is busy */
wait_82802ab(flash);
/* Read identifier codes */
chip_writeb(flash, 0x90, bios);
/* Read master lock-bit */
mcfg = chip_readb(flash, bios + 0x3);
msg_cdbg("master lock is ");
if (mcfg) {
msg_cdbg("locked!\n");
} else {
msg_cdbg("unlocked!\n");
can_unlock = 1;
}
/* Read block lock-bits, 8 * 8 KB + 15 * 64 KB */
for (i = 0; i < flash->chip->total_size * 1024;
i += (i >= (64 * 1024) ? 64 * 1024 : 8 * 1024)) {
bcfg = chip_readb(flash, bios + i + 2); /* read block lock config */
msg_cdbg("block lock at %06x is %slocked!\n", i,
bcfg ? "" : "un");
if (bcfg)
need_unlock = 1;
}
/* Reset chip */
chip_writeb(flash, 0xFF, bios);
/* Unlock: clear block lock-bits, if needed */
if (can_unlock && need_unlock) {
msg_cdbg("Unlock: ");
chip_writeb(flash, 0x60, bios);
chip_writeb(flash, 0xD0, bios);
chip_writeb(flash, 0xFF, bios);
wait_82802ab(flash);
msg_cdbg("Done!\n");
}
/* Error: master locked or a block is locked */
if (!can_unlock && need_unlock) {
msg_cerr("At least one block is locked and lockdown is active!\n");
return -1;
}
return 0;
}
int printlock_w39v040a(struct flashchip *flash)
{
uint8_t lock;
int ret = 0;
/* The W39V040A datasheet contradicts itself on the lock register
* location: 0x00002 and 0x7fff2 are both mentioned. Pick the one
* which is similar to the other chips of the same family.
*/
lock = w39_idmode_readb(flash, 0x7fff2);
msg_cdbg("Lockout bits:\n");
ret = printlock_w39_tblwp(lock);
ret |= printlock_w39_bootblock_64k16k(lock);
return ret;
}
int unlock_28f004s5(struct flashctx *flash)
{
chipaddr bios = flash->virtual_memory;
uint8_t mcfg, bcfg, need_unlock = 0, can_unlock = 0;
int i;
/* Clear status register */
chip_writeb(flash, 0x50, bios);
/* Read identifier codes */
chip_writeb(flash, 0x90, bios);
/* Read master lock-bit */
mcfg = chip_readb(flash, bios + 0x3);
msg_cdbg("master lock is ");
if (mcfg) {
msg_cdbg("locked!\n");
} else {
msg_cdbg("unlocked!\n");
can_unlock = 1;
}
/* Read block lock-bits */
for (i = 0; i < flash->chip->total_size * 1024; i+= (64 * 1024)) {
bcfg = chip_readb(flash, bios + i + 2); // read block lock config
msg_cdbg("block lock at %06x is %slocked!\n", i, bcfg ? "" : "un");
if (bcfg) {
need_unlock = 1;
}
}
/* Reset chip */
chip_writeb(flash, 0xFF, bios);
/* Unlock: clear block lock-bits, if needed */
if (can_unlock && need_unlock) {
msg_cdbg("Unlock: ");
chip_writeb(flash, 0x60, bios);
chip_writeb(flash, 0xD0, bios);
chip_writeb(flash, 0xFF, bios);
msg_cdbg("Done!\n");
}
/* Error: master locked or a block is locked */
if (!can_unlock && need_unlock) {
msg_cerr("At least one block is locked and lockdown is active!\n");
return -1;
}
return 0;
}
static int unlock_w39_fwh_block(struct flashchip *flash, int offset)
{
chipaddr wrprotect = flash->virtual_registers + offset + 2;
uint8_t locking;
locking = chip_readb(wrprotect);
/* Read or write lock present? */
if (locking & ((1 << 2) | (1 << 0))) {
/* Lockdown active? */
if (locking & (1 << 1)) {
msg_cerr("Can't unlock block at 0x%x!\n", offset);
return -1;
} else {
msg_cdbg("Unlocking block at 0x%x\n", offset);
chip_writeb(0, wrprotect);
}
}
return 0;
}
static int printlock_w39_fwh_block(struct flashchip *flash, int offset)
{
chipaddr wrprotect = flash->virtual_registers + offset + 2;
uint8_t locking;
locking = chip_readb(wrprotect);
msg_cdbg("Lock status of block at 0x%08x is ", offset);
switch (locking & 0x7) {
case 0:
msg_cdbg("Full Access.\n");
break;
case 1:
msg_cdbg("Write Lock (Default State).\n");
break;
case 2:
msg_cdbg("Locked Open (Full Access, Lock Down).\n");
break;
case 3:
msg_cerr("Error: Write Lock, Locked Down.\n");
break;
case 4:
msg_cdbg("Read Lock.\n");
break;
case 5:
msg_cdbg("Read/Write Lock.\n");
break;
case 6:
msg_cerr("Error: Read Lock, Locked Down.\n");
break;
case 7:
msg_cerr("Error: Read/Write Lock, Locked Down.\n");
break;
}
/* Read or write lock present? */
return (locking & ((1 << 2) | (1 << 0))) ? -1 : 0;
}
