/*
* Clear hardware registers after Apps powers up.
*/
static void msm_pm_config_hw_after_power_up(void)
{
if (cpu_is_msm7x30() || cpu_is_msm8x55()) {
__raw_writel(0, APPS_SECOP);
mb();
__raw_writel(0, APPS_PWRDOWN);
mb();
msm_spm_reinit();
} else if (cpu_is_msm8625()) {
__raw_writel(0, APPS_PWRDOWN);
mb();
if (power_collapsed) {
/*
* enable the SCU while coming out of power
* collapse.
*/
scu_enable(MSM_SCU_BASE);
/*
* Program the top csr to put the core1 into GDFS.
*/
configure_top_csr();
}
} else {
__raw_writel(0, APPS_PWRDOWN);
mb();
__raw_writel(0, APPS_CLK_SLEEP_EN);
mb();
}
}
/*
* Clear hardware registers after Apps powers up.
*/
static void msm_pm_config_hw_after_power_up(void)
{
#if defined(CONFIG_ARCH_MSM7X30)
writel(0, APPS_SECOP);
writel(0, APPS_PWRDOWN);
msm_spm_reinit();
#else
writel(0, APPS_PWRDOWN);
writel(0, APPS_CLK_SLEEP_EN);
#endif
}
/*
* Program the top csr from core0 context to put the
* core1 into GDFS, as core1 is not running yet.
*/
static void configure_top_csr(void)
{
void __iomem *base_ptr;
unsigned int value = 0;
base_ptr = core1_reset_base();
if (!base_ptr)
return;
/* bring the core1 out of reset */
__raw_writel(0x3, base_ptr);
mb();
/*
* override DBGNOPOWERDN and program the GDFS
* count val
*/
__raw_writel(0x00030002, (MSM_CFG_CTL_BASE + 0x38));
mb();
/* Initialize the SPM0 and SPM1 registers */
msm_spm_reinit();
/* enable TCSR for core1 */
value = __raw_readl((MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG));
value |= BIT(22);
__raw_writel(value, MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG);
mb();
/* set reset bit for SPM1 */
value = __raw_readl((MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG));
value |= BIT(20);
__raw_writel(value, MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG);
mb();
/* set CLK_OFF bit */
value = __raw_readl((MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG));
value |= BIT(18);
__raw_writel(value, MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG);
mb();
/* set clamps bit */
value = __raw_readl((MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG));
value |= BIT(21);
__raw_writel(value, MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG);
mb();
/* set power_up bit */
value = __raw_readl((MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG));
value |= BIT(19);
__raw_writel(value, MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG);
mb();
/* Disable TSCR for core0 */
value = __raw_readl((MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG));
value &= ~BIT(22);
__raw_writel(value, MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG);
mb();
__raw_writel(0x0, base_ptr);
mb();
}
