void msm_vidc_free_platform_resources(
struct msm_vidc_platform_resources *res)
{
msm_vidc_free_clock_table(res);
msm_vidc_free_regulator_table(res);
msm_vidc_free_freq_table(res);
msm_vidc_free_reg_table(res);
msm_vidc_free_bus_vectors(res);
msm_vidc_free_iommu_groups(res);
}
static int msm_vidc_load_reg_table(struct msm_vidc_platform_resources *res)
{
struct reg_set *reg_set;
struct platform_device *pdev = res->pdev;
int i;
int rc = 0;
if (!of_find_property(pdev->dev.of_node, "qcom,reg-presets", NULL)) {
/* qcom,reg-presets is an optional property. It likely won't be
* present if we don't have any register settings to program */
dprintk(VIDC_DBG, "qcom,reg-presets not found\n");
return 0;
}
reg_set = &res->reg_set;
reg_set->count = get_u32_array_num_elements(pdev, "qcom,reg-presets");
reg_set->count /= sizeof(*reg_set->reg_tbl) / sizeof(u32);
if (reg_set->count == 0) {
dprintk(VIDC_DBG, "no elements in reg set\n");
return rc;
}
reg_set->reg_tbl = devm_kzalloc(&pdev->dev, reg_set->count *
sizeof(*(reg_set->reg_tbl)), GFP_KERNEL);
if (!reg_set->reg_tbl) {
dprintk(VIDC_ERR, "%s Failed to alloc register table\n",
__func__);
return -ENOMEM;
}
if (of_property_read_u32_array(pdev->dev.of_node, "qcom,reg-presets",
(u32 *)reg_set->reg_tbl, reg_set->count * 2)) {
dprintk(VIDC_ERR, "Failed to read register table\n");
msm_vidc_free_reg_table(res);
return -EINVAL;
}
for (i = 0; i < reg_set->count; i++) {
dprintk(VIDC_DBG,
"reg = %x, value = %x\n",
reg_set->reg_tbl[i].reg,
reg_set->reg_tbl[i].value
);
}
return rc;
}
