int buffaloBoardInfoInit(void)
{
extern u32 env_addr;
extern u32 env_size;
char *p = ioremap(env_addr + env_size - 1024, 1024);
if (p) {
buffalo_product_id = __be32_to_cpu(ioread32(p + 4));
strncpy(buffalo_series_name,p + 0x10, BUF_NV_SIZE_SERIES_NAME);
buffalo_series_name[BUF_NV_SIZE_SERIES_NAME - 1] = '\0';
strncpy(buffalo_product_name,p + 0x30, BUF_NV_SIZE_PRODUCT_NAME);
buffalo_product_name[BUF_NV_SIZE_PRODUCT_NAME - 1] = '\0';
}
if (buffalo_product_id == 0x0 || buffalo_product_id == 0xffffffff)
buffalo_product_id = 0x0000200B;
if (strlen(buffalo_series_name) == 0)
strcpy(buffalo_series_name,"TeraStation");
if (strlen(buffalo_product_name) == 0)
strcpy(buffalo_product_name,"TS-XL/R5");
mvGppPolaritySet(0, 0xffffffff, MV_GPP_IN_ORIGIN);
mvGppPolaritySet(0, (1 << 14)|(1 << 15)|(1 << 16)|(1 << 17)|(1 << 18)|(1 << 19), MV_GPP_IN_INVERT);
return 0;
}
/* GPIO Settings for Back voltage problem workaround */
MV_U8 mvUsbGppInit(int dev)
{
MV_U32 regVal;
MV_U8 gppNo = (MV_U8)mvBoardUSBVbusGpioPinGet(dev);
MV_U8 gppVbusEnNo = (MV_U8)mvBoardUSBVbusEnGpioPinGet(dev);
/* DDR1 => gpp5, DDR2 => gpp1 */
if(gppNo != (MV_U8)N_A)
{
/*mvOsPrintf("mvUsbGppInit: gppNo=%d\n", gppNo);*/
/* MPP Control Register - set to GPP*/
regVal = MV_REG_READ(mvCtrlMppRegGet((unsigned int)(gppNo/8)));
regVal &= ~(0xf << ((gppNo%8)*4));
MV_REG_WRITE(mvCtrlMppRegGet((unsigned int)(gppNo/8)), regVal);
if(gppNo < 32)
{
/* GPIO Data Out Enable Control Register - set to input*/
mvGppTypeSet(0, (1<<gppNo), MV_GPP_IN & (1<<gppNo) );
/* GPIO Data In Polarity Register */
mvGppPolaritySet(0, (1<<gppNo), (0<<gppNo) );
}
else
{
/* GPIO Data Out Enable Control Register - set to input*/
mvGppTypeSet(1, (1<<(gppNo-32)), MV_GPP_IN & (1<<(gppNo-32)) );
/* GPIO Data In Polarity Register */
mvGppPolaritySet(1, (1<<(gppNo-32)), (0<<(gppNo-32)) );
}
/* GPIO Data In Polarity Register */
/* mvGppPolaritySet(mppGrp, (1<<gppNo), (0<<gppNo) ); */
regVal = MV_REG_READ(MV_USB_PHY_POWER_CTRL_REG(dev));
regVal &= ~(7 << 24);
MV_REG_WRITE(MV_USB_PHY_POWER_CTRL_REG(dev), regVal);
}
/* for device - reset vbus enable gpp, for host - set by default */
if(gppVbusEnNo != (MV_U8)N_A)
{
/*mvOsPrintf("mvUsbGppInit: gppVbusEnNo = %d \n", gppVbusEnNo);*/
regVal = MV_REG_READ(GPP_DATA_OUT_REG((gppVbusEnNo/32)));
if(gppVbusEnNo < 32)
{
MV_REG_WRITE(GPP_DATA_OUT_REG(0), (regVal & ~(1 << gppVbusEnNo)));
}
else
{
MV_REG_WRITE(GPP_DATA_OUT_REG(1), (regVal & ~(1 << (gppVbusEnNo - 32))));
}
}
return gppNo;
}
int mvUsbBackVoltageUpdate(int dev, MV_U8 gppNo)
{
int vbusChange = 0;
MV_U32 gppData, regVal, gppInv;
if(gppNo < 32)
{
gppInv = mvGppPolarityGet(0, (1 << gppNo));
gppData = mvGppValueGet(0, (1 << gppNo));
}
else
{
gppInv = mvGppPolarityGet(1, (1 << (gppNo-32)));
gppData = mvGppValueGet(1, (1 << (gppNo-32)));
}
regVal = MV_REG_READ(MV_USB_PHY_POWER_CTRL_REG(dev));
if( (gppInv == 0) &&
(gppData != 0) )
{
/* VBUS appear */
regVal |= (7 << 24);
if(gppNo < 32)
gppInv |= (1 << gppNo);
else
gppInv |= (1 << (gppNo-32));
/*mvOsPrintf("VBUS appear: dev=%d, gpp=%d\n", dev, gppNo);*/
vbusChange = 1;
}
else if( (gppInv != 0) &&
(gppData != 0) )
{
/* VBUS disappear */
regVal &= ~(7 << 24);
if(gppNo < 32)
gppInv &= ~(1 << gppNo);
else
gppInv &= ~(1 << (gppNo-32));
/*mvOsPrintf("VBUS disappear: dev=%d, gpp=%d\n", dev, gppNo);*/
vbusChange = 2;
}
else
{
/* No changes */
return vbusChange;
}
MV_REG_WRITE(MV_USB_PHY_POWER_CTRL_REG(dev), regVal);
if(gppNo < 32)
mvGppPolaritySet(0, (1<<gppNo), gppInv);
else
mvGppPolaritySet(1, (1<<(gppNo-32)), gppInv);
return vbusChange;
}
static int
resetSataHotplugDev(struct sata_hotplug_data *data)
{
int pinNum = (int)data->dev_id;
if (data->lastplugstat == SATA_STAT_UNPLUGGED) {
if(pinNum < 32)
mvGppPolaritySet(0, BIT(pinNum), initial_polarity_val);
else
mvGppPolaritySet(1, BIT(pinNum - 32), initial_polarity_val_high);
}
else {
if(pinNum < 32)
mvGppPolaritySet(0, BIT(pinNum), ~initial_polarity_val);
else
mvGppPolaritySet(1, BIT(pinNum - 32), ~initial_polarity_val_high);
}
return 0;
}
MV_VOID mvBoardEnvInit(MV_VOID)
{
MV_U32 boardId= mvBoardIdGet();
if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
{
mvOsPrintf("mvBoardEnvInit:Board unknown.\n");
return;
}
if (mvBoardIdGet() != XCAT98DX_ID) {
/* Set NAND interface access parameters */
MV_REG_WRITE(NAND_READ_PARAMS_REG, BOARD_INFO(boardId)->nandFlashReadParams);
MV_REG_WRITE(NAND_WRITE_PARAMS_REG, BOARD_INFO(boardId)->nandFlashWriteParams);
MV_REG_WRITE(NAND_CTRL_REG, BOARD_INFO(boardId)->nandFlashControl);
}
/* Set GPP Out value */
MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow);
MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValHigh);
/* set GPP polarity */
mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow);
mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh);
/* Workaround for Erratum FE-MISC-70*/
if(mvCtrlRevGet()==MV_88F6XXX_A0_REV)
{
BOARD_INFO(boardId)->gppOutEnValLow &= 0xfffffffd;
BOARD_INFO(boardId)->gppOutEnValLow |= (BOARD_INFO(boardId)->gppOutEnValHigh) & 0x00000002;
} /*End of WA*/
/* Set GPP Out Enable*/
mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow);
mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh);
/* Nand CE */
MV_REG_BIT_SET(NAND_CTRL_REG, NAND_ACTCEBOOT_BIT);
}
void __init mv_init_irq(void)
{
u32 gppMask,i;
#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X)
coreId = whoAmI();
printk("IRQ initialize for core %d\n", coreId);
#endif
/* Disable all interrupts initially. */
if (0 == coreId)
{
MV_REG_WRITE(GPP_INT_MASK_REG(0), 0);
MV_REG_WRITE(GPP_INT_LVL_REG(0), 0);
}
MV_REG_WRITE(CPU_INT_MASK_LOW_REG(coreId), 0);
MV_REG_WRITE(CPU_INT_MASK_HIGH_REG(coreId), 0);
/* Set Gpp interrupts as needed */
if (0 == coreId) /*GPP for core 0 only*/
{
gppMask = mvBoardGpioIntMaskGet();
mvGppTypeSet(0, gppMask , (MV_GPP_IN & gppMask));
mvGppPolaritySet(0, gppMask , (MV_GPP_IN_INVERT & gppMask));
/* clear all int */
MV_REG_WRITE(GPP_INT_MASK_REG(0), 0);
MV_REG_WRITE(CPU_INT_MASK_HIGH_REG(coreId), IRQ_GPP_MASK);
}
else
MV_REG_WRITE(CPU_INT_MASK_HIGH_REG(coreId), 0);
/* Do the core module ones */
for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &mv_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
/* TBD. Add support for error interrupts */
return;
}
void __init mv_init_irq(void)
{
u32 gppMask,i;
/* Set Gpp interrupts as needed */
gppMask = mvBoardGpioIntMaskGet();
//jack20060626 mark
//mvGppOutEnablle(0, gppMask , (MV_GPP_IN & gppMask));
mvGppPolaritySet(0, gppMask , (MV_GPP_IN_INVERT & gppMask));
/* Disable all interrupts initially. */
MV_REG_WRITE(MV_IRQ_MASK_REG, 0x0);
MV_REG_WRITE(MV_GPP_IRQ_MASK_REG, 0x0);
/* enable GPP in the main cause */
MV_REG_BIT_SET(MV_IRQ_MASK_REG, (1 << IRQ_GPP_0_7) | (1 << IRQ_GPP_8_15));
#if defined(CONFIG_ARCH_MV88f5181)
MV_REG_BIT_SET(MV_IRQ_MASK_REG, (1 << IRQ_GPP_16_23) | (1 << IRQ_GPP_24_31));
#endif
/* clear all int */
MV_REG_WRITE(MV_IRQ_CAUSE_REG, 0x0);
MV_REG_WRITE(MV_GPP_IRQ_CAUSE_REG, 0x0);
/* Do the core module ones */
for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &mv_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
/* TBD. Add support for error interrupts */
return;
}
//----------------------------------------------------------------------
// RTC
//----------------------------------------------------------------------
void BuffaloGpio_RtcIntSetup(void)
{
mvGppTypeSet(0, BIT(BIT_RTC) , BIT(BIT_RTC)); // disable output
mvGppPolaritySet(0, BIT(BIT_RTC) , 0);
MV_REG_WRITE(GPP_INT_LVL_REG(0), 0);
}