MV_VOID mvEth1121PhyBasicInit(MV_U32 phyAddr)
{
MV_U16 value;
/* Change page select to 2 */
value = 2;
mvEthPhyRegWrite(phyAddr, 22, value);
mvOsDelay(10);
/* Set RGMII rx delay */
mvEthPhyRegRead(phyAddr, 21, &value);
value |= BIT5;
mvEthPhyRegWrite(phyAddr, 21, value);
mvOsDelay(10);
/* Change page select to 0 */
value = 0;
mvEthPhyRegWrite(phyAddr, 22, value);
mvOsDelay(10);
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, &value);
value |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, value);
mvOsDelay(10);
}
MV_VOID mvEth1121PhyBasicInit(MV_U32 port)
{
MV_U16 value;
MV_U16 phyAddr = mvBoardPhyAddrGet(port);
MV_REG_WRITE(ETH_PHY_ADDR_REG(port), phyAddr);
/* Change page select to 2 */
value = 2;
mvEthPhyRegWrite(phyAddr, 22, value);
mvOsDelay(10);
/* Set RGMII rx delay */
mvEthPhyRegRead(phyAddr, 21, &value);
value |= BIT5;
mvEthPhyRegWrite(phyAddr, 21, value);
mvOsDelay(10);
/* Change page select to 0 */
value = 0;
mvEthPhyRegWrite(phyAddr, 22, value);
mvOsDelay(10);
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, &value);
value |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, value);
mvOsDelay(10);
}
/******************************************************************************
* mvEthCompSwitchReset
*
* DESCRIPTION:
* Reset switch device after being configured by ethernet complex functions.
*
* INPUT:
* ethCompCfg - Ethernet complex configuration bitmap.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_OK on success,
* MV_ERROR otherwise.
*******************************************************************************/
MV_STATUS mvEthCompSwitchReset(MV_U32 ethCompCfg)
{
MV_U32 reg;
MV_U32 i;
if (!(ethCompCfg & (ESC_OPT_MAC0_2_SW_P4 | ESC_OPT_MAC1_2_SW_P5))) {
/* If no switch is connected, then we need to enable the 25MHz
** clock, and get the switch out of reset
*/
/* Set switch phy address so it does not collide with other
** addresses.
*/
reg = MV_REG_READ(MV_ETHCOMP_CTRL_REG(1));
reg &= ~ETHCC_SWTCH_ADDR_MASK;
reg |= (0xF << ETHCC_SWTCH_ADDR_OFFSET);
MV_REG_WRITE(MV_ETHCOMP_CTRL_REG(1), reg);
MV_REG_BIT_SET(MV_ETHCOMP_CTRL_REG(0), (1 << ETHCC_SW_FI_125_CLK_OFFSET));
MV_REG_BIT_SET(MV_ETHCOMP_CTRL_REG(1), ETHCC_SWTCH_RESET_MASK);
return MV_OK;
}
/* Disable polling on MAC ports. */
if (ethCompCfg & ESC_OPT_MAC0_2_SW_P4)
MV_REG_BIT_RESET(ETH_UNIT_CONTROL_REG(0), BIT1);
if (ethCompCfg & ESC_OPT_MAC1_2_SW_P5)
MV_REG_BIT_RESET(ETH_UNIT_CONTROL_REG(1), BIT1);
/*
* 3.1.4. Reset de-assertion:
* 3.1.4.1. De-assert Switch reset: set Regunit
* Ethernet_Complex_Control_1 register, field SwitchReset to 0x1.
*/
MV_REG_BIT_SET(MV_ETHCOMP_CTRL_REG(1), ETHCC_SWTCH_RESET_MASK);
#warning "Fix this to poll the Switch EEInt after reset"
mvOsDelay(100);
/* 10Mbps support */
for (i = 1; i < 4; i++) {
reg = MV_REG_READ(MV_ETHCOMP_CTRL_REG(3));
reg |= ETHCC_SW_PX_FRC_MII_SPD_MASK(i);
MV_REG_WRITE(MV_ETHCOMP_CTRL_REG(3), reg);
mvOsDelay(1);
reg |= ETHCC_SW_PX_FRC_SPD_MASK(i);
MV_REG_WRITE(MV_ETHCOMP_CTRL_REG(3), reg);
mvOsDelay(1);
reg &= ~ETHCC_SW_PX_FRC_MII_SPD_MASK(i);
MV_REG_WRITE(MV_ETHCOMP_CTRL_REG(3), reg);
mvOsDelay(1);
reg &= ~ETHCC_SW_PX_FRC_SPD_MASK(i);
MV_REG_WRITE(MV_ETHCOMP_CTRL_REG(3), reg);
mvOsDelay(1);
}
return MV_OK;
}
/*******************************************************************************
* twsiIntFlgClr - Clear Interrupt flag.
*
* DESCRIPTION:
* This routine clears the interrupt flag. It does NOT poll the interrupt
* to make sure the clear. After clearing the interrupt, it waits for at
* least 1 miliseconds.
*
* INPUT:
* chanNum - TWSI channel
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
static MV_VOID twsiIntFlgClr(MV_U8 chanNum)
{
MV_U32 temp;
/* wait for 1 mili to prevent TWSI register write after write problems */
mvOsDelay(1);
/* clear the int flag bit */
temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum));
MV_REG_WRITE(TWSI_CONTROL_REG(chanNum),temp & ~(TWSI_CONTROL_INT_FLAG_SET));
/* wait for 1 mili sec for the clear to take effect */
mvOsDelay(1);
return;
}
/*******************************************************************************
* mvAc97Reset
*
* DESCRIPTION:
* Cold reset the AC'97 unit.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_OK - On successfull init,
* MV_FAIL - If initialization fails.
*******************************************************************************/
MV_STATUS mvAc97Reset(MV_VOID)
{
//MV_U32 timeout = 1000;
/* Hold CLKBPB for 100us */
MV_REG_BIT_RESET(MV_AC97_GLOBAL_CTRL_REG,AC97_GLB_CTRL_COLD_RESET_MASK);
MV_REG_BIT_SET(MV_AC97_GLOBAL_CTRL_REG,AC97_GLB_CTRL_INT_CLK_EN_MASK);
mvOsUDelay(100);
MV_REG_BIT_RESET(MV_AC97_GLOBAL_CTRL_REG,AC97_GLB_CTRL_INT_CLK_EN_MASK);
MV_REG_BIT_SET(MV_AC97_GLOBAL_CTRL_REG,AC97_GLB_CTRL_COLD_RESET_MASK);
#if 0 /* Not sure if this is needed. */
MV_REG_BIT_SET(MV_AC97_GLOBAL_CTRL_REG,
AC97_GLB_CTRL_COLD_RESET_MASK | AC97_GLB_CTRL_WARM_RESET_MASK);
while(timeout > 0) {
val = MV_REG_READ(MV_AC97_GLOBAL_STATUS_REG);
if(val & (AC97_GLB_PCODEC_READY_MASK | AC97_GLB_SCODEC_READY_MASK))
break;
timeout--;
mvOsDelay(10);
}
if(timeout == 0)
return MV_TIMEOUT;
#endif /* 0 */
return MV_OK;
}
void daaCalibration(unsigned int daa_dev)
{
unsigned char reg17;
mvOsPrintf("Start ADC calibration\n");
/* Set CALD bit */
reg17 = readDaaDirectReg(daa_dev, DAA_INTERNATIONAL_CONTROL_2);
writeDaaDirectReg(daa_dev, DAA_INTERNATIONAL_CONTROL_2, (reg17 | DAA_CALD));
/* Set MCAL bit */
reg17 = readDaaDirectReg(daa_dev, DAA_INTERNATIONAL_CONTROL_2);
writeDaaDirectReg(daa_dev, DAA_INTERNATIONAL_CONTROL_2, (reg17 | DAA_MCAL));
/* Reset MCAL bit - start ADC calibration */
reg17 = readDaaDirectReg(daa_dev, DAA_INTERNATIONAL_CONTROL_2);
writeDaaDirectReg(daa_dev, DAA_INTERNATIONAL_CONTROL_2, (reg17 & ~DAA_MCAL));
/* Must wait at least 256 ms */
mvOsDelay(300);
mvOsPrintf("ADC calibration completed\n");
}
static MV_STATUS resetSensor(MV_CAM_SENSOR *pCamSensor)
{
MV_STATUS status = mvSysCamSensorRegWrite(pCamSensor->I2CClient,
OV_REG_12, 1 << 7);
mvOsDelay(2);
return status;
}
/*******************************************************************************
* mvEthE6131PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* ethPortNum - Ethernet port number
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE6131SwitchBasicInit(MV_U32 ethPortNum)
{
MV_U16 reg;
/*Enable Phy power up*/
mvEthPhyRegWrite (0,0,0x9140);
mvEthPhyRegWrite (1,0,0x9140);
mvEthPhyRegWrite (2,0,0x9140);
/*Enable PPU*/
mvEthPhyRegWrite (0x1b,4,0x4080);
/*Enable Phy detection*/
mvEthPhyRegRead (0x13,0,®);
reg &= ~(1<<12);
mvEthPhyRegWrite (0x13,0,reg);
mvOsDelay(100);
mvEthPhyRegWrite (0x13,1,0x33);
switchVlanInit(ethPortNum,
MV_E6131_CPU_PORT,
MV_E6131_MAX_PORTS_NUM,
MV_E6131_PORTS_OFFSET,
MV_E6131_ENABLED_PORTS);
}
/*******************************************************************************
* mvSysTdmInit - Initialize the TDM subsystem
*
* DESCRIPTION:
*
* INPUT:
* None
* OUTPUT:
* None
* RETURN:
* None
*
*******************************************************************************/
MV_STATUS mvSysTdmInit(MV_TDM_PARAMS* tdmParams)
{
MV_TDM_HAL_DATA halData;
MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1];
MV_STATUS status;
status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1);
if(status == MV_OK)
#ifdef MV_TDM_SUPPORT
status = mvTdmWinInit(addrWinMap);
#else
status = mvCommUnitWinInit(addrWinMap);
#endif
if(status == MV_OK) {
halData.spiMode = mvBoardTdmSpiModeGet();
halData.model = mvCtrlModelGet();
#ifdef MV_TDM_SUPPORT
status = mvTdmHalInit (tdmParams, &halData);
#else
halData.maxCs = mvBoardTdmDevicesCountGet();
status = mvCommUnitHalInit (tdmParams, &halData);
/* Issue SLIC reset */
mvGppValueSet(0, BIT25, 0);
mvOsDelay(1);
mvGppValueSet(0, BIT25, BIT25);
#endif
}
return status;
}
/******************************************************************************
* mvEthCompSwTo3FePhyConfig
*
* DESCRIPTION:
* Configure ethernet complex for Switch ports 1-4 to 3xFE output.
*
* INPUT:
* ethCompCfg - Ethernet complex configuration bitmap.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_OK on success,
* MV_ERROR otherwise.
*******************************************************************************/
MV_STATUS mvEthCompSwTo3FePhyConfig(MV_U32 ethCompCfg)
{
MV_U32 reg;
MV_U32 i;
if (!(ethCompCfg & ESC_OPT_FE3PHY))
return MV_OK;
/* 3.7. Switch P1,2 & 3 to FE-PHY (10Mbps/ 100 Mbps) */
/* 3.7.2. Ethernet-Complex configuration :
* 3.7.2.2. Connect Switch ports 1,2 & 3 to FE-PPHY ports 0,1 & 2: set
* Regunit Ethernet_Complex_Control_0 register, field
* SwitchPort123Source to "FEPHY" (0x1).
*/
reg = MV_REG_READ(MV_ETHCOMP_CTRL_REG(0));
reg &= ~ETHCC_SW_PORT_123_SRC_MASK;
reg |= (0x1 << ETHCC_SW_PORT_123_SRC_OFFSET);
MV_REG_WRITE(MV_ETHCOMP_CTRL_REG(0), reg);
/* 3.7.2.3. Enable Switch and FE-PHY TX clock, by setting speed to 25MHz
* (this is needed due to design bug): set Regunit Ethernet Complex
* Control 3 register, fields "SwPort1ForceSpeed",
* "SwPort1ForceMiiSpeed", "SwPort2ForceSpeed", "SwPort2ForceMiiSpeed",
* "SwPort3ForceSpeed" and "SwPort3ForceMiiSpeed" to force MII-100,
* i.e. 25MHz TX clock. All these fields should be set to 0x1.
*/
reg = MV_REG_READ(MV_ETHCOMP_CTRL_REG(3));
for (i = 1; i < 4; i++) {
reg &= ~ETHCC_SW_PX_FRC_SPD_MASK(i);
/* reg |= ETHCC_SW_PX_FRC_MII_SPD_MASK(i); */
}
MV_REG_WRITE(MV_ETHCOMP_CTRL_REG(3), reg);
/* 3.7.3. Reset de-assertion:
* 3.7.3.1. De-assert F-PHY reset: set Regunit FE PHY Control 0
* register, field "fe_phy_pd_reset_a" to Normal mode (0x1).
*/
reg = MV_REG_READ(MV_ETHCOMP_FE_PHY_CTRL_REG);
for (i = 0; i < 3; i++)
reg |= (0x3 << ETHCC_FE_PHY_AN_MODE_OFFSET(i));
MV_REG_BIT_RESET(MV_ETHCOMP_CTRL_REG(3), ETHCC_FEPHY_TX_DATA_SMPL_MASK);
/* Enable FE Phy Crossover */
reg |= (0x1 << ETHCC_FE_PHY_XOVER_EN_OFFSET);
MV_REG_WRITE(MV_ETHCOMP_FE_PHY_CTRL_REG, reg);
MV_REG_BIT_RESET(MV_ETHCOMP_FE_PHY_CTRL_REG, ETHCC_FE_PHY_RESET_MASK);
mvOsDelay(100);
MV_REG_BIT_SET(MV_ETHCOMP_FE_PHY_CTRL_REG, ETHCC_FE_PHY_RESET_MASK);
return MV_OK;
}
/*******************************************************************************
* twsiAckBitSet - Set acknowledge bit on the bus
*
* DESCRIPTION:
* This routine set the acknowledge bit on the TWSI bus.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
static MV_VOID twsiAckBitSet(MV_U8 chanNum)
{
MV_U32 temp;
/*Set the Ack bit */
temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum));
MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_ACK);
/* Add delay of 1ms */
mvOsDelay(1);
return;
}
/*******************************************************************************
* mvEth1145PhyInit - Initialize MARVELL 1145 Phy
*
* DESCRIPTION:
*
* INPUT:
* phyAddr - Phy address.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvEth1145PhyBasicInit(MV_U32 phyAddr)
{
MV_U16 value;
/* Set Link1000 output pin to be link indication, set Tx output pin to be activity */
mvEthPhyRegWrite(phyAddr, 0x18, ETH_PHY_LED_ACT_LNK_DV);
mvOsDelay(10);
/* Add delay to RGMII Tx and Rx */
mvEthPhyRegRead(phyAddr, 0x14, &value);
mvEthPhyRegWrite(phyAddr, 0x14, (value | BIT1 | BIT7));
mvOsDelay(10);
/* Set Phy TPVL to 0 */
mvEthPhyRegWrite(phyAddr, 0x10, 0x60);
mvOsDelay(10);
/* Reset Phy */
mvEthPhyRegRead(phyAddr, 0x00, &value);
mvEthPhyRegWrite(phyAddr, 0x00, (value | BIT15));
mvOsDelay(10);
return;
}
static void mvEthComplexMacToSwPort(MV_U32 port, MV_U32 swPort,
MV_BOARD_MAC_SPEED speed)
{
MV_U32 src;
mvEthComplexSwResetSet(MV_FALSE);
mvOsDelay(200);
src = mvEthComplexSwPortSrcCalc(swPort, ETHC_SW_PORT_SRC_GBE_MAC);
mvEthComplexSwPortSrcSet(swPort, src);
mvEthComplexGbePortSrcSet(port, 0x1);
/* GE MAC #0 - Switch Port6 2G Speed */
if (port == 0 && swPort == 6 && speed == BOARD_MAC_SPEED_2000M) {
mvEthComplexGbeToSwitchSpeedSet(speed);
mvEthComplexPortDpClkSrcSet(port, 0x0);
} else
mvEthComplexPortDpClkSrcSet(port, 0x1);
}
MV_VOID mvEthInternalGEPhyBasicInit(MV_U32 phyAddr)
{
MV_U16 value;
if (ethphyHalData.ctrlRevId < 2) {
mvEthPhyRegWrite(phyAddr, 0x16, 0x00FF);
mvEthPhyRegWrite(phyAddr, 0x11, 0x0FD0);
mvEthPhyRegWrite(phyAddr, 0x10, 0x214C);
mvEthPhyRegWrite(phyAddr, 0x11, 0x0000);
mvEthPhyRegWrite(phyAddr, 0x10, 0x2000);
mvEthPhyRegWrite(phyAddr, 0x11, 0x0F16);
mvEthPhyRegWrite(phyAddr, 0x10, 0x2146);
mvEthPhyRegWrite(phyAddr, 0x16, 0x0);
}
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, &value);
value |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, value);
mvOsDelay(10);
return;
}
static int mvEgigaInit(struct eth_device *dev, bd_t *p)
{
egigaPriv *priv = dev->priv;
MV_STATUS status;
int i, phys_queue, phys_port;
MV_BOARD_MAC_SPEED mac_speed;
MV_ETH_PORT_SPEED speed = 0;
MV_32 phy_addr;
static MV_U8 mac_bcast[6] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
mv_eth_bm_start();
/* init each port only once */
if (priv->devInit != MV_TRUE) {
/* port power up - release from reset */
if (!MV_PP2_IS_PON_PORT(priv->port)) {
phy_addr = mvBoardPhyAddrGet(priv->port);
if (phy_addr != -1) {
mvGmacPhyAddrSet(priv->port, phy_addr);
mvEthPhyInit(priv->port, MV_FALSE);
}
mvGmacPortPowerUp(priv->port,
mvBoardIsPortInSgmii(priv->port),
MV_FALSE/*mvBoardIsPortInRgmii(priv->port)*/);
}
/* init the hal -- create internal port control structure and descriptor rings, */
/* open address decode windows, disable rx and tx operations. mask interrupts. */
priv->halPriv = mvPp2PortInit(priv->port, priv->port * CONFIG_MV_ETH_RXQ, CONFIG_MV_ETH_RXQ, NULL);
if (!priv->halPriv) {
printf("falied to init eth port (error)\n");
goto error;
}
/* after init port - init rx & tx */
MV_PP2_PHYS_RXQ_CTRL *rxqCtrl = mvPp2RxqInit(priv->port, EGIGA_DEF_RXQ, EGIGA_RXQ_LEN);
if (!rxqCtrl) {
printf("Rxq Init Failed\n");
goto error;
}
MV_PP2_PHYS_TXQ_CTRL *txqCtrl =
mvPp2TxqInit(priv->port, EGIGA_DEF_TXP, EGIGA_DEF_TXQ, EGIGA_TXQ_LEN, EGIGA_TXQ_HWF_LEN);
if (!txqCtrl) {
printf("Txq Init Failed\n");
goto error;
}
mvPp2RxqBmLongPoolSet(priv->port, EGIGA_DEF_RXQ, EGIGA_BM_POOL);
mvPp2RxqBmShortPoolSet(priv->port, EGIGA_DEF_RXQ, EGIGA_BM_POOL);
mvPp2RxqNonOccupDescAdd(priv->port, EGIGA_DEF_RXQ, EGIGA_RXQ_LEN);
mvPp2TxpMaxTxSizeSet(priv->port, EGIGA_DEF_TXP, RX_PKT_SIZE);
priv->devInit = MV_TRUE;
}
mac_speed = mvBoardMacSpeedGet(priv->port);
if (mac_speed != BOARD_MAC_SPEED_AUTO) {
switch (mac_speed) {
case BOARD_MAC_SPEED_10M:
speed = MV_ETH_SPEED_10;
break;
case BOARD_MAC_SPEED_100M:
speed = MV_ETH_SPEED_100;
break;
case BOARD_MAC_SPEED_1000M:
case BOARD_MAC_SPEED_2000M:
speed = MV_ETH_SPEED_1000;
break;
default:
/* do nothing */
break;
}
if (mvGmacForceLinkModeSet(priv->port, MV_TRUE, MV_FALSE)) {
printf("mvEthForceLinkModeSet failed\n");
goto error;
}
if (mvGmacSpeedDuplexSet(priv->port, speed, MV_ETH_DUPLEX_FULL)) {
printf("mvEthSpeedDuplexSet failed\n");
goto error;
}
if (mvGmacFlowCtrlSet(priv->port, MV_ETH_FC_DISABLE)) {
printf("mvEthFlowCtrlSet failed\n");
goto error;
}
}
/* allow new packets to RXQs */
mvPp2PortIngressEnable(priv->port, 1);
/* classifier port default config */
phys_queue = mvPp2LogicRxqToPhysRxq(priv->port, EGIGA_DEF_RXQ);
phys_port = MV_PPV2_PORT_PHYS(priv->port);
mvPp2ClsHwPortDefConfig(phys_port, 0, FLOWID_DEF(phys_port), phys_queue);
if (mvPrsMacDaAccept(phys_port, mac_bcast, 1 /*add*/)) {
printf("%s: mvPrsMacDaAccept failed\n", dev->name);
return -1;
}
if (mvPrsMacDaAccept(phys_port, dev->enetaddr, 1 /*add*/)) {
printf("%s: mvPrsMacDaAccept failed\n", dev->name);
return -1;
}
if (mvPrsDefFlow(phys_port)) {
printf("%s: mvPp2PrsDefFlow failed\n", dev->name);
return -1;
}
/* start the hal - rx/tx activity */
/* Check if link is up for 2 Sec */
for (i = 1; i < 100; i++) {
status = mvPp2PortEnable(priv->port, 1);
if (status == MV_OK) {
priv->devEnable = MV_TRUE;
break;
}
mvOsDelay(20);
}
if (status != MV_OK) {
printf("%s: %s mvPp2PortEnable failed (error)\n", __func__, dev->name);
goto error;
}
mvPp2PortEgressEnable(priv->port, 1);
return 1;
error:
if (priv->devInit)
mvEgigaHalt(dev);
printf("%s: %s failed\n", __func__, dev->name);
return -1;
}
MV_STATUS mvPexHalInit(MV_U32 pexIf, MV_PEX_TYPE pexType)
{
MV_PEX_MODE pexMode;
MV_U32 regVal;
MV_U32 status;
/* First implement Guideline (GL# PCI Express-2) Wrong Default Value */
/* to Transmitter Output Current (TXAMP) Relevant for: 88F5181-A1/B0/B1 */
/* and 88F5281-B0 and above, 88F5182, 88F5082, 88F5181L, 88F6082/L */
if ((mvCtrlModelGet() != MV_1281_DEV_ID) &&
(mvCtrlModelGet() != MV_6281_DEV_ID) &&
(mvCtrlModelGet() != MV_6192_DEV_ID) &&
(mvCtrlModelGet() != MV_6190_DEV_ID) &&
(mvCtrlModelGet() != MV_6180_DEV_ID) &&
(mvCtrlModelGet() != MV_6183_DEV_ID) &&
(mvCtrlModelGet() != MV_6183L_DEV_ID) &&
(mvCtrlModelGet() != MV_78100_DEV_ID) &&
(mvCtrlModelGet() != MV_78200_DEV_ID) &&
(mvCtrlModelGet() != MV_76100_DEV_ID) &&
(mvCtrlModelGet() != MV_78XX0_DEV_ID))
{
/* Read current value of TXAMP */
MV_REG_WRITE(0x41b00, 0x80820000); /* Write the read command */
regVal = MV_REG_READ(0x41b00); /* Extract the data */
/* Prepare new data for write */
regVal &= ~0x7; /* Clear bits [2:0] */
regVal |= 0x4; /* Set the new value */
regVal &= ~0x80000000; /* Set "write" command */
MV_REG_WRITE(0x41b00, regVal); /* Write the write command */
}
else
{
/* Implement 1.0V termination GL for 88F1281 device only */
/* BIT0 - Common mode feedback */
/* BIT3 - TxBuf, extra drive for 1.0V termination */
if (mvCtrlModelGet() == MV_1281_DEV_ID)
{
MV_REG_WRITE(0x41b00, 0x80860000); /* Write the read command */
regVal = MV_REG_READ(0x41b00); /* Extract the data */
regVal |= (BIT0 | BIT3);
regVal &= ~0x80000000; /* Set "write" command */
MV_REG_WRITE(0x41b00, regVal); /* Write the write command */
MV_REG_WRITE(0x31b00, 0x80860000); /* Write the read command */
regVal = MV_REG_READ(0x31b00); /* Extract the data */
regVal |= (BIT0 | BIT3);
regVal &= ~0x80000000; /* Set "write" command */
MV_REG_WRITE(0x31b00, regVal); /* Write the write command */
}
}
if( mvPexModeGet(pexIf, &pexMode) != MV_OK)
{
mvOsPrintf("PEX init ERR. mvPexModeGet failed (pexType=%d)\n",pexMode.pexType);
return MV_ERROR;
}
/* Check that required PEX type is the one set in reset time */
if (pexType != pexMode.pexType)
{
/* No Link. Shut down the Phy */
mvPexPowerDown(pexIf);
mvOsPrintf("PEX init ERR. PEX type sampled mismatch (%d,%d)\n",pexType,pexMode.pexType);
return MV_ERROR;
}
if (MV_PEX_ROOT_COMPLEX == pexType)
{
mvPexLocalBusNumSet(pexIf, PEX_HOST_BUS_NUM(pexIf));
mvPexLocalDevNumSet(pexIf, PEX_HOST_DEV_NUM(pexIf));
/* Local device master Enable */
mvPexMasterEnable(pexIf, MV_TRUE);
/* Local device slave Enable */
mvPexSlaveEnable(pexIf, mvPexLocalBusNumGet(pexIf),
mvPexLocalDevNumGet(pexIf), MV_TRUE);
/* Interrupt disable */
status = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_STATUS_AND_COMMAND));
status |= PXSAC_INT_DIS;
MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_STATUS_AND_COMMAND), status);
}
/* now wait 500 ms to be sure the link is valid (spec compliant) */
mvOsDelay(500);
/* Check if we have link */
if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN)
{
mvOsPrintf("PEX%d interface detected no Link.\n",pexIf);
return MV_NO_SUCH;
}
if (MV_PEX_WITDH_X1 == pexMode.pexWidth)
{
mvOsPrintf("PEX%d interface detected Link X1\n",pexIf);
}
else
{
mvOsPrintf("PEX%d interface detected Link X4\n",pexIf);
}
#ifdef PCIE_VIRTUAL_BRIDGE_SUPPORT
mvPexVrtBrgInit(pexIf);
#endif
return MV_OK;
}
MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType, MV_PEX_HAL_DATA *halData)
{
MV_PEX_MODE pexMode;
MV_U32 regVal;
MV_U32 status;
MV_U16 ctrlModel, phyRegVal;
mvOsMemcpy(&pexHalData[pexIf], halData, sizeof(MV_PEX_HAL_DATA));
/* First implement Guideline (GL# PCI Express-2) Wrong Default Value */
/* to Transmitter Output Current (TXAMP) Relevant for: 88F5181-A1/B0/B1 */
/* and 88F5281-B0 and above, 88F5182, 88F5082, 88F5181L, 88F6082/L */
ctrlModel = pexHalData[pexIf].ctrlModel;
if ((ctrlModel != MV_1281_DEV_ID) &&
(ctrlModel != MV_6281_DEV_ID) &&
(ctrlModel != MV_6282_DEV_ID) &&
(ctrlModel != MV_6280_DEV_ID) &&
(ctrlModel != MV_6192_DEV_ID) &&
(ctrlModel != MV_6190_DEV_ID) &&
(ctrlModel != MV_6180_DEV_ID) &&
(ctrlModel != MV_6183_DEV_ID) &&
(ctrlModel != MV_6183L_DEV_ID) &&
(ctrlModel != MV_78100_DEV_ID) &&
(ctrlModel != MV_78200_DEV_ID) &&
(ctrlModel != MV_76100_DEV_ID) &&
(ctrlModel != MV_6323_DEV_ID) &&
(ctrlModel != MV_6322_DEV_ID) &&
(ctrlModel != MV_6321_DEV_ID) &&
(ctrlModel != MV_78XX0_DEV_ID) &&
(ctrlModel != MV_6510_DEV_ID) &&
(ctrlModel != MV_6530_DEV_ID) &&
(ctrlModel != MV_6550_DEV_ID) &&
(ctrlModel != MV_6560_DEV_ID) &&
(ctrlModel != MV_6710_DEV_ID) &&
(ctrlModel != MV_78130_DEV_ID) &&
(ctrlModel != MV_78160_DEV_ID) &&
(ctrlModel != MV_78230_DEV_ID) &&
(ctrlModel != MV_78260_DEV_ID) &&
(ctrlModel != MV_78460_DEV_ID) &&
(ctrlModel != MV_78000_DEV_ID)) {
/* Read current value of TXAMP */
MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), 0x80820000); /* Write the read command */
regVal = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf)); /* Extract the data */
/* Prepare new data for write */
regVal &= ~0x7; /* Clear bits [2:0] */
regVal |= 0x4; /* Set the new value */
regVal &= ~0x80000000; /* Set "write" command */
MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regVal); /* Write the write command */
} else {
/* Implement 1.0V termination GL for 88F1281 device only */
/* BIT0 - Common mode feedback */
/* BIT3 - TxBuf, extra drive for 1.0V termination */
if (ctrlModel == MV_1281_DEV_ID) {
MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), 0x80860000); /* Write the read command */
regVal = MV_REG_READ(0x41b00); /* Extract the data */
regVal |= (BIT0 | BIT3);
regVal &= ~0x80000000; /* Set "write" command */
MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regVal); /* Write the write command */
MV_REG_WRITE(0x31b00, 0x80860000); /* Write the read command */
regVal = MV_REG_READ(0x31b00); /* Extract the data */
regVal |= (BIT0 | BIT3);
regVal &= ~0x80000000; /* Set "write" command */
MV_REG_WRITE(0x31b00, regVal); /* Write the write command */
}
}
if ((ctrlModel == MV_6281_DEV_ID) ||
(ctrlModel == MV_6282_DEV_ID) ||
(ctrlModel == MV_6280_DEV_ID) ||
(ctrlModel == MV_6192_DEV_ID) ||
(ctrlModel == MV_6190_DEV_ID) ||
(ctrlModel == MV_6180_DEV_ID)) {
regVal = MV_REG_READ(0x100e4); /* This register currently doesn't appear in the FS */
regVal |= 0x3 << 25;
MV_REG_WRITE(0x100e4, regVal);
}
if (ctrlModel == MV_6282_DEV_ID) {
mvPexPhyRegRead(pexIf, 0x92, &phyRegVal);
phyRegVal &= ~(0x80F0);
phyRegVal |= 0x8080;
mvPexPhyRegWrite(pexIf, 0x92, phyRegVal);
} else if ((ctrlModel == MV_6510_DEV_ID) ||
(ctrlModel == MV_6530_DEV_ID) || (ctrlModel == MV_6550_DEV_ID) || (ctrlModel == MV_6560_DEV_ID)) {
regVal = MV_REG_READ(0x100e4); /* This register currently doesn't appear in the FS */
regVal |= 0x3 << 25;
MV_REG_WRITE(0x100e4, regVal);
mvPexPhyRegRead(pexIf, 0x92, &phyRegVal);
phyRegVal &= ~(0x80F0);
phyRegVal |= 0x8080;
mvPexPhyRegWrite(pexIf, 0x92, phyRegVal);
}
if (mvPexModeGet(pexIf, &pexMode) != MV_OK) {
mvOsPrintf("PEX init ERR. mvPexModeGet failed (pexType=%d)\n", pexMode.pexType);
return MV_ERROR;
}
/* Check that required PEX type is the one set in reset time */
if (pexType != pexMode.pexType) {
/* No Link. Shut down the Phy */
mvPexPhyPowerDown(pexIf);
mvOsPrintf("PEX init ERR. PEX type sampled mismatch (%d,%d)\n", pexType, pexMode.pexType);
return MV_ERROR;
}
if (MV_PEX_ROOT_COMPLEX == pexType) {
mvPexLocalBusNumSet(pexIf, PEX_HOST_BUS_NUM(pexIf));
mvPexLocalDevNumSet(pexIf, PEX_HOST_DEV_NUM(pexIf));
/* Local device master Enable */
mvPexMasterEnable(pexIf, MV_TRUE);
/* Local device slave Enable */
mvPexSlaveEnable(pexIf, mvPexLocalBusNumGet(pexIf), mvPexLocalDevNumGet(pexIf), MV_TRUE);
/* Interrupt disable */
status = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_STATUS_AND_COMMAND));
status |= PXSAC_INT_DIS;
MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_STATUS_AND_COMMAND), status);
if (ctrlModel == MV_6710_DEV_ID) {
/* PEX capability */
regVal = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CAPABILITY_REG)) & 0xF;
if (regVal == 0x2) {
/* KW40 set to Gen 2.0 - conf_auto_speed_change */
/* when bit is set, link will issue link speed change to the max link speed possible */
regVal = MV_REG_READ(PEX_CTRL_REG(pexIf)) | (1<<10);
MV_REG_WRITE(PEX_CTRL_REG(pexIf), regVal);
}
}
} else {
/* TODO: 14/12/10 - requested by CV to support EP Compliance */
MV_REG_WRITE(PEX_DBG_CTRL_REG(pexIf), 0x0F62F0C0);
MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), (0x80C2 << 16));
regVal = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf)) & 0xFFFF;
MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), (0xC2 << 16) | regVal | (1 << 2));
MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), (0x8080 << 16));
regVal = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf)) & 0xFFFF;
MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), (0x80 << 16) | regVal | (0x2 << 1));
}
mvSysPexCpuIfEnable(pexIf);
/* now wait 1ms to be sure the link is valid */
mvOsDelay(100);
/* Check if we have link */
if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN) {
/*mvOsPrintf("PEX%d interface detected no Link.\n", pexIf);*/
return MV_NO_SUCH;
}
#if 0
if (MV_PEX_WITDH_X1 == pexMode.pexWidth)
mvOsPrintf("PEX%d interface detected Link X1\n", pexIf);
else
mvOsPrintf("PEX%d interface detected Link X4\n", pexIf);
#endif
#ifdef PCIE_VIRTUAL_BRIDGE_SUPPORT
mvPexVrtBrgInit(pexIf);
#endif
return MV_OK;
}
int initDaa(unsigned int *daaDev, unsigned int ch, int workMode, int intMode)
{
unsigned char reg2 = 0, reg24;
long newDelay;
MV_DAA_DEV *pDaaDev;
int lineSideId;
pDaaDev = (MV_DAA_DEV *)mvOsMalloc(sizeof(MV_DAA_DEV));
if(!pDaaDev)
{
mvOsPrintf("%s: error malloc failed\n",__FUNCTION__);
return 1;
}
work_mode = workMode;
interrupt_mode = intMode;
pDaaDev->ch = ch;
if(work_mode)
pDaaDev->dcval = ch + 1;
pDaaDev->hook = 0;
pDaaDev->ring = 0;
pDaaDev->reverse_polarity = 0;
pDaaDev->drop_out = 0;
*daaDev = (unsigned int)pDaaDev;
/* Software reset */
writeDaaDirectReg(*daaDev, 1, 0x80);
/* Wait just a bit */
mvOsDelay(100);
setDaaDigitalHybrid(COUNTRY_INDEX, *daaDev);
/* Set Transmit/Receive timeslot */
/* Configure tx/rx sample in DAA */
pDaaDev->txSample = ((pDaaDev->ch==0) ? CH0_TX_SLOT : CH1_TX_SLOT);
pDaaDev->rxSample = ((pDaaDev->ch==0) ? CH0_RX_SLOT : CH1_RX_SLOT);
mvOsPrintf("FXO-%d: RX sample %d, TX sample %d\n",pDaaDev->ch, pDaaDev->rxSample, pDaaDev->txSample);
pDaaDev->txSample *= 8;
pDaaDev->rxSample *= 8;
setDaaPcmStartCountRegs(*daaDev);
#ifdef MV_TDM_LINEAR_MODE
/* Enable PCM, linear 16 bit */
writeDaaDirectReg(*daaDev, 33, 0x38);
#else
/* Enable PCM, m-Law 8 bit */
writeDaaDirectReg(*daaDev, 33, 0x28);
#endif
/* Enable full wave rectifier */
writeDaaDirectReg(*daaDev, DAA_INTERNATIONAL_CONTROL_3, DAA_RFWE);
/* Disable interrupts */
disableDaaInterrupts(*daaDev);
/* Set AOUT/INT pin as hardware interrupt */
reg2 = readDaaDirectReg(*daaDev, DAA_CONTROL_2_REG);
writeDaaDirectReg(*daaDev, DAA_CONTROL_2_REG, (reg2 | DAA_INTE));
/* Enable ISO-Cap */
writeDaaDirectReg(*daaDev, DAA_DAA_CONTROL_2, 0);
/* Wait 2000ms for ISO-cap to come up */
newDelay = 2000;
while(newDelay > 0 && !(readDaaDirectReg(*daaDev, DAA_SYSTEM_AND_LINE_SIDE_REV_REG) & 0xf0))
{
mvOsDelay(100);
newDelay -= 100;
}
lineSideId = readDaaDirectReg(*daaDev, DAA_SYSTEM_AND_LINE_SIDE_REV_REG);
if (!(lineSideId & 0xf0)) {
mvOsPrintf("Error: FXO did not bring up ISO link properly!\n");
return 1;
}
/* Perform ADC manual calibration */
daaCalibration(*daaDev);
/* Enable Ring Validation */
reg24 = readDaaDirectReg(*daaDev, DAA_RING_VALIDATION_CONTROL_3);
writeDaaDirectReg(*daaDev,DAA_RING_VALIDATION_CONTROL_3 , reg24 | DAA_RNGV);
/* Print DAA info */
printDaaInfo(*daaDev);
TRC_REC("ISO-Cap is now up, line side: %02x rev %02x\n",
readDaaDirectReg(*daaDev, 11) >> 4,
( readDaaDirectReg(*daaDev, 13) >> 2) & 0xf);
/* raise tx gain by 7 dB for NEWZEALAND */
if (!strcmp(daa_modes[COUNTRY_INDEX].name, "NEWZEALAND")) {
mvOsPrintf("Adjusting gain\n");
writeDaaDirectReg(*daaDev, 38, 0x7);
}
return 0;
}
int BattOn(int vbhIn, int vblIn, int vbpIn)
{
uint8 data[20] = { 0 };
int i;
uint16 vbhTarget;
uint16 vblTarget;
uint16 vbpTarget;
uint8 vbhHex;
uint8 vblHex;
uint8 vbpHex;
uint8 calVbhHex;
uint8 calVblHex;
uint8 calVbpHex;
/* Argument checking */
if (vblIn > 0) {
mvOsPrintf(" VBL must be negative or zero\n");
return -1;
}
if (vbhIn > 0) {
mvOsPrintf(" VBH must be negative or zero\n");
return -1;
}
if (vbpIn < 0) {
mvOsPrintf(" VBP must be positive or zero\n");
return -1;
}
if (vblIn - vbhIn < 5 && vblIn != 0) {
mvOsPrintf(" VBH must be at least 5V more negative than VBL\n");
return -1;
}
/* 16 no-ops to clear MPI buffer */
for (i = 0; i < 16; i++)
data[i] = VP880_NO_OP;
VpMpiCmd(gDev1Id, EC_BOTH, VP880_NO_OP, 16, data);
VpMpiCmd(gDev2Id, EC_BOTH, VP880_NO_OP, 16, data);
/* Read RCN/PCN and check that the devices are what we expect */
VpMpiCmd(gDev1Id, EC_BOTH, VP880_DEVTYPE_CMD, VP880_DEVTYPE_LEN, data);
if (data[0] != VP880_REV_JE || data[1] != VP880_DEV_PCN_88506) {
mvOsPrintf("Invalid device 1, RCN/PCN 0x%02X%02X\n", data[0], data[1]);
return -1;
}
VpMpiCmd(gDev2Id, EC_BOTH, VP880_DEVTYPE_CMD, VP880_DEVTYPE_LEN, data);
if (data[0] != VP880_REV_JE || data[1] != VP880_DEV_PCN_88506) {
mvOsPrintf("Invalid device 2, RCN/PCN 0x%02X%02X\n", data[0], data[1]);
return -1;
}
/* Run MPI checks on both devices to make sure that it's safe to start
* programming the devices. If the signal integrity is bad, it could be
* dangerous to continue. */
if (MpiTest(gDev1Id) < 0 || MpiTest(gDev2Id) < 0)
return -1;
/* HW reset */
VpMpiCmd(gDev1Id, EC_BOTH, VP880_HW_RESET_CMD, 0, NULL);
VpMpiCmd(gDev2Id, EC_BOTH, VP880_HW_RESET_CMD, 0, NULL);
/* Configure 8.192MHz mclk */
data[0] = 0x8A;
VpMpiCmd(gDev1Id, EC_BOTH, VP880_MCLK_CNT_WRT, VP880_MCLK_CNT_LEN, data);
VpMpiCmd(gDev2Id, EC_BOTH, VP880_MCLK_CNT_WRT, VP880_MCLK_CNT_LEN, data);
/* Unmask CFAIL */
data[0] = 0xFF & ~(VP880_CFAIL_MASK);
data[1] = 0xFF;
VpMpiCmd(gDev1Id, EC_BOTH, VP880_INT_MASK_WRT, VP880_INT_MASK_LEN, data);
VpMpiCmd(gDev2Id, EC_BOTH, VP880_INT_MASK_WRT, VP880_INT_MASK_LEN, data);
/* Make sure CFAIL clears on both devices */
for (i = 0; i < 11; i++) {
VpMpiCmd(gDev1Id, EC_BOTH, VP880_UL_SIGREG_RD, VP880_UL_SIGREG_LEN, data);
if ((data[0] & VP880_CFAIL_MASK) == 0)
break;
if (i == 10) {
mvOsPrintf("Couldn't clear CFAIL on dev 1");
return -1;
}
mvOsDelay(10);
}
for (i = 0; i < 11; i++) {
VpMpiCmd(gDev2Id, EC_BOTH, VP880_UL_SIGREG_RD, VP880_UL_SIGREG_LEN, data);
if ((data[0] & VP880_CFAIL_MASK) == 0)
break;
if (i == 10) {
mvOsPrintf("Couldn't clear CFAIL on dev 2");
return -1;
}
mvOsDelay(10);
}
/* Set the switcher timings */
data[0] = 0xB2; /* Device defaults */
data[1] = 0x00;
data[2] = 0xB1;
data[3] = 0x00;
data[4] = 0xB0;
data[5] = 0x40;
VpMpiCmd(gDev1Id, EC_BOTH, VP880_INT_SWREG_PARAM_WRT, VP880_INT_SWREG_PARAM_LEN, data);
VpMpiCmd(gDev2Id, EC_BOTH, VP880_INT_SWREG_PARAM_WRT, VP880_INT_SWREG_PARAM_LEN, data);
/* ICR2 settings: c_tip_on and c_ring_on for measuring in disconnect,
* 150V battery limit */
data[0] = VP880_ICR2_TIP_SENSE | VP880_ICR2_RING_SENSE;
data[1] = VP880_ICR2_TIP_SENSE | VP880_ICR2_RING_SENSE;
data[2] = VP880_ICR2_SWY_LIM_CTRL | VP880_ICR2_SWY_LIM_CTRL1;
data[3] = VP880_ICR2_SWY_LIM_CTRL | VP880_ICR2_SWY_LIM_CTRL1;
VpMpiCmd(gDev1Id, EC_BOTH, VP880_ICR2_WRT, VP880_ICR2_LEN, data);
VpMpiCmd(gDev2Id, EC_BOTH, VP880_ICR2_WRT, VP880_ICR2_LEN, data);
/* ICR3 settings: VREF ctrl, "line block control circuitry override" for
* measuring in disconnect */
data[0] = VP880_ICR3_VREF_CTRL | VP880_ICR3_LINE_CTRL;
data[1] = VP880_ICR3_VREF_CTRL | VP880_ICR3_LINE_CTRL;
data[2] = 0;
data[3] = 0;
VpMpiCmd(gDev1Id, EC_BOTH, VP880_ICR3_WRT, VP880_ICR3_LEN, data);
VpMpiCmd(gDev2Id, EC_BOTH, VP880_ICR3_WRT, VP880_ICR3_LEN, data);
/* ICR4 settings: voice ADC override for measuring in disconnect */
data[0] = VP880_ICR4_VOICE_ADC_CTRL;
data[1] = VP880_ICR4_VOICE_ADC_CTRL;
data[2] = 0;
data[3] = 0;
VpMpiCmd(gDev1Id, EC_BOTH, VP880_ICR4_WRT, VP880_ICR4_LEN, data);
VpMpiCmd(gDev2Id, EC_BOTH, VP880_ICR4_WRT, VP880_ICR4_LEN, data);
/* Wait for VREF to stabilize */
mvOsDelay(20);
/* Disable auto system state ctrl, zero cross ringing, auto clock fail
* switching, and thermal fault switching. Enable auto battery shutdown */
data[0] = VP880_ACFS_DIS | VP880_ATFS_DIS | VP880_ZXR_DIS | VP880_AUTO_SSC_DIS | VP880_AUTO_BAT_SHUTDOWN_EN;
VpMpiCmd(gDev1Id, EC_BOTH, VP880_SS_CONFIG_WRT, VP880_SS_CONFIG_LEN, data);
VpMpiCmd(gDev2Id, EC_BOTH, VP880_SS_CONFIG_WRT, VP880_SS_CONFIG_LEN, data);
/* Zero out signal generator params for the channel (ch2 on dev1) that will
* be in ringing */
for (i = 0; i < VP880_SIGA_PARAMS_LEN; i++)
data[i] = 0;
VpMpiCmd(gDev1Id, EC_2, VP880_SIGA_PARAMS_WRT, VP880_SIGA_PARAMS_LEN, data);
/* Calculate the register settings. Calculations are performed based on
* units of cV and unsigned, for example -65.3 V == 6530 */
vbhTarget = (ABS(vbhIn) * 100);
vblTarget = (ABS(vblIn) * 100);
vbpTarget = (ABS(vbpIn) * 100);
DBG("VBH Calibration:\n");
CalculateRegisters(vbhTarget, gVbhCalAry, &vbhHex, &calVbhHex);
DBG("VBH results, vbhHex %02X, calVbhHex %02X\n\n", vbhHex, calVbhHex);
DBG("VBL Calibration:\n");
CalculateRegisters(vblTarget, gVblCalAry, &vblHex, &calVblHex);
DBG("VBL results, vblHex %02X, calVblHex %02X\n\n", vblHex, calVblHex);
DBG("VBP Calibration:\n");
CalculateRegisters(vbpTarget, gVbpCalAry, &vbpHex, &calVbpHex);
DBG("VBP results, vbpHex %02X, calVbpHex %02X\n\n", vbpHex, calVbpHex);
/* Set up switching regulator params - fixed, programmable */
data[0] = VP880_FLYBACK_MODE | VP880_ZRING_TRACK_DIS | VP880_YRING_TRACK_DIS;
data[1] = VP880_SWY_AUTOPOWER_DIS | vbhHex;
data[2] = VP880_SWZ_AUTOPOWER_DIS | vblHex;
VpMpiCmd(gDev1Id, EC_BOTH, VP880_REGULATOR_PARAM_WRT, VP880_REGULATOR_PARAM_LEN, data);
data[0] = VP880_FLYBACK_MODE | VP880_ZRING_TRACK_DIS | VP880_YRING_TRACK_DIS;
data[1] = VP880_SWY_AUTOPOWER_DIS | vbpHex;
data[2] = VP880_SWZ_AUTOPOWER_DIS;
VpMpiCmd(gDev2Id, EC_BOTH, VP880_REGULATOR_PARAM_WRT, VP880_REGULATOR_PARAM_LEN, data);
/* Set battery calibration registers */
data[1] = 0;
data[0] = calVbhHex << 3;
VpMpiCmd(gDev1Id, EC_1, VP880_BAT_CALIBRATION_WRT, VP880_BAT_CALIBRATION_LEN, data);
data[0] = calVblHex << 3;
VpMpiCmd(gDev1Id, EC_2, VP880_BAT_CALIBRATION_WRT, VP880_BAT_CALIBRATION_LEN, data);
data[0] = calVbpHex << 3;
VpMpiCmd(gDev2Id, EC_1, VP880_BAT_CALIBRATION_WRT, VP880_BAT_CALIBRATION_LEN, data);
/* Disable high-pass filter, cut off TX/RX */
data[0] = VP880_HIGH_PASS_DIS | VP880_CUT_TXPATH | VP880_CUT_RXPATH;
VpMpiCmd(gDev1Id, EC_BOTH, VP880_OP_COND_WRT, VP880_OP_COND_LEN, data);
VpMpiCmd(gDev2Id, EC_BOTH, VP880_OP_COND_WRT, VP880_OP_COND_LEN, data);
/* Set to linear mode, use default filters */
data[0] = VP880_LINEAR_CODEC | VP880_DEFAULT_OP_FUNC_MODE;
VpMpiCmd(gDev1Id, EC_BOTH, VP880_OP_FUNC_WRT, VP880_OP_FUNC_LEN, data);
VpMpiCmd(gDev2Id, EC_BOTH, VP880_OP_FUNC_WRT, VP880_OP_FUNC_LEN, data);
/* Set default DISN (00) */
data[0] = VP880_DEFAULT_DISN_GAIN;
VpMpiCmd(gDev1Id, EC_BOTH, VP880_DISN_WRT, VP880_DISN_LEN, data);
VpMpiCmd(gDev2Id, EC_BOTH, VP880_DISN_WRT, VP880_DISN_LEN, data);
mvOsDelay(50);
/*** Bring up HBAT ***/
/* Set HBAT switcher to low power. */
data[0] = 0;
if (vbhTarget != 0)
data[0] |= VP880_SWY_LP;
VpMpiCmd(gDev1Id, EC_BOTH, VP880_REGULATOR_CTRL_WRT, VP880_REGULATOR_CTRL_LEN, data);
mvOsDelay(10);
/* Set the line state:
* Dev 1 ch 1: disconnect (switcher Y)
* Disconnect is needed so that the voltages don't track to VOC */
data[0] = VP880_SS_DISCONNECT | VP880_SS_ACTIVATE_MASK;
VpMpiCmd(gDev1Id, EC_1, VP880_SYS_STATE_WRT, VP880_SYS_STATE_LEN, data);
mvOsDelay(100);
/*** Bring up LBAT ***/
/* Do a read/modify/write of ICR2 to override the LBAT switcher (Z) to off
* so that we can set the line state to ringing before turning it on */
VpMpiCmd(gDev1Id, EC_2, VP880_ICR2_RD, VP880_ICR2_LEN, data);
data[2] |= VP880_ICR2_SWY_CTRL_EN;
data[3] &= ~VP880_ICR2_SWY_CTRL_EN;
VpMpiCmd(gDev1Id, EC_2, VP880_ICR2_WRT, VP880_ICR2_LEN, data);
/* Set the switcher control to low power. It won't actually turn on yet
* because of the ICR2 command above, but setting the register will allow
* the line state to be set to ringing. */
VpMpiCmd(gDev1Id, EC_BOTH, VP880_REGULATOR_CTRL_RD, VP880_REGULATOR_CTRL_LEN, data);
data[0] = 0;
if (vblTarget != 0)
data[0] |= VP880_SWZ_LP;
VpMpiCmd(gDev1Id, EC_BOTH, VP880_REGULATOR_CTRL_WRT, VP880_REGULATOR_CTRL_LEN, data);
mvOsDelay(10);
/* Set the line state:
* Dev 1 ch 2: ringing (switcher Z) */
data[0] = VP880_SS_BALANCED_RINGING;
VpMpiCmd(gDev1Id, EC_2, VP880_SYS_STATE_WRT, VP880_SYS_STATE_LEN, data);
mvOsDelay(10);
/* Turn the switcher on */
VpMpiCmd(gDev1Id, EC_2, VP880_ICR2_RD, VP880_ICR2_LEN, data);
data[2] |= VP880_ICR2_SWY_CTRL_EN;
data[3] |= VP880_ICR2_SWY_CTRL_EN;
VpMpiCmd(gDev1Id, EC_2, VP880_ICR2_WRT, VP880_ICR2_LEN, data);
mvOsDelay(100);
/*** Bring up PBAT ***/
/* Set PBAT switcher to low power. */
data[0] = 0;
if (vbpTarget != 0)
data[0] |= VP880_SWY_LP;
VpMpiCmd(gDev2Id, EC_BOTH, VP880_REGULATOR_CTRL_WRT, VP880_REGULATOR_CTRL_LEN, data);
mvOsDelay(10);
/* Set the line states:
* Dev 2 ch 1: disconnect (switcher Y)
* Disconnect is needed so that the voltages don't track to VOC */
data[0] = VP880_SS_DISCONNECT | VP880_SS_ACTIVATE_MASK;
VpMpiCmd(gDev2Id, EC_1, VP880_SYS_STATE_WRT, VP880_SYS_STATE_LEN, data);
mvOsDelay(100);
/* Set switchers to high power for non-zero batteries, one at a time */
VpMpiCmd(gDev1Id, EC_BOTH, VP880_REGULATOR_CTRL_RD, VP880_REGULATOR_CTRL_LEN, data);
if (vbhTarget != 0) {
data[0] &= ~VP880_SWY_MODE_MASK;
data[0] |= VP880_SWY_HP;
VpMpiCmd(gDev1Id, EC_BOTH, VP880_REGULATOR_CTRL_WRT, VP880_REGULATOR_CTRL_LEN, data);
}
mvOsDelay(20);
if (vblTarget != 0) {
data[0] &= ~VP880_SWZ_MODE_MASK;
data[0] |= VP880_SWZ_HP;
VpMpiCmd(gDev1Id, EC_BOTH, VP880_REGULATOR_CTRL_WRT, VP880_REGULATOR_CTRL_LEN, data);
}
mvOsDelay(20);
data[0] = 0;
if (vbpTarget != 0) {
data[0] |= VP880_SWY_HP;
VpMpiCmd(gDev2Id, EC_BOTH, VP880_REGULATOR_CTRL_WRT, VP880_REGULATOR_CTRL_LEN, data);
}
/* Set IOs to outputs to control the module LEDs */
data[0] = VP880_IODIR_IO1_OUTPUT | VP880_IODIR_IO2_OUTPUT;
VpMpiCmd(gDev1Id, EC_BOTH, VP880_IODIR_REG_WRT, VP880_IODIR_REG_LEN, data);
VpMpiCmd(gDev2Id, EC_BOTH, VP880_IODIR_REG_WRT, VP880_IODIR_REG_LEN, data);
/* Turn on the LEDs for non-zero batteries. */
data[0] = 0;
if (vbhTarget != 0) {
/* gDev1Id IO1 controls the VBH (v1) LED */
data[0] |= VP880_IODATA_IO1;
}
if (vblTarget != 0) {
/* gDev1Id IO2 controls the VBL (v2) LED */
data[0] |= VP880_IODATA_IO2;
}
VpMpiCmd(gDev1Id, EC_1, VP880_IODATA_REG_WRT, VP880_IODATA_REG_LEN, data);
data[0] = 0;
if (vbpTarget != 0) {
/* gDev2Id IO1 controls the VBP (v3) LED */
data[0] |= VP880_IODATA_IO1;
}
VpMpiCmd(gDev2Id, EC_1, VP880_IODATA_REG_WRT, VP880_IODATA_REG_LEN, data);
mvOsPrintf("Power supply initialized successfully\n");
return 0;
}
/******************************************************************************
* mvEthCompMac2SwitchConfig
*
* DESCRIPTION:
* Configure ethernet complex for MAC0/1 to switch ports 5/6 mode.
*
* INPUT:
* ethCompCfg - Ethernet complex configuration bitmap.
* muxCfgOnly - MV_TRUE: Configure only the ethernet complex mux'es and
* skip other switch reset configurations.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_OK on success,
* MV_ERROR otherwise.
*******************************************************************************/
MV_STATUS mvEthCompMac2SwitchConfig(MV_U32 ethCompCfg, MV_BOOL muxCfgOnly)
{
MV_U32 reg, portEnabled = 0;
if (!(ethCompCfg & (ESC_OPT_MAC0_2_SW_P4 | ESC_OPT_MAC1_2_SW_P5)))
return MV_OK;
/* GbE-MAC-0 to Switch P4 (1000Mbps) */
/* GbE-MAC-1 to Switch P5 (1000Mbps) */
if (muxCfgOnly == MV_FALSE) {
/* Set switch phy address */
reg = MV_REG_READ(MV_ETHCOMP_CTRL_REG(1));
reg &= ~ETHCC_SWTCH_ADDR_MASK;
if (ethCompCfg & ESC_OPT_MAC0_2_SW_P4)
reg |= (mvBoardPhyAddrGet(0) << ETHCC_SWTCH_ADDR_OFFSET);
else
reg |= (mvBoardPhyAddrGet(1) << ETHCC_SWTCH_ADDR_OFFSET);
MV_REG_WRITE(MV_ETHCOMP_CTRL_REG(1), reg);
/*
* 3.1.2. Switch power-on configurations:
* 3.1.2.1. Activate Switch ports 1-6 (1 bit per port): set Regunit
* Ethernet_Complex_Control_2 register, field SwitchPortState, to 0x7E.
*/
reg = MV_REG_READ(MV_ETHCOMP_CTRL_REG(2));
reg &= ~ETHCC_SW_PRT_STATE_MASK;
if (ethCompCfg & ESC_OPT_RGMIIA_SW_P5)
portEnabled |= BIT5;
if (ethCompCfg & ESC_OPT_RGMIIA_SW_P6)
portEnabled |= BIT6;
if (ethCompCfg & ESC_OPT_MAC0_2_SW_P4)
portEnabled |= BIT4;
if (ethCompCfg & ESC_OPT_MAC1_2_SW_P5)
portEnabled |= BIT5;
if (ethCompCfg & ESC_OPT_GEPHY_SW_P0)
portEnabled |= BIT0;
if (ethCompCfg & ESC_OPT_GEPHY_SW_P5)
portEnabled |= BIT5;
if (ethCompCfg & ESC_OPT_FE3PHY)
portEnabled |= BIT1 | BIT2 | BIT3;
if (ethCompCfg & ESC_OPT_QSGMII)
portEnabled |= BIT0 | BIT1 | BIT2 | BIT3;
portEnabled |= BIT4 | BIT5;
reg |= (portEnabled << ETHCC_SW_PRT_STATE_OFFSET); /* 0x7E */
MV_REG_WRITE(MV_ETHCOMP_CTRL_REG(2), reg);
/* 3.1.3. Ethernet-Complex configuration:
* 3.1.3.1. Configure Switch 125Mhz clock source: set
* Regunit Ethernet_Complex_Control_0 register, field SwFi125ClkSrc to
* MiscPLL (0x1).
*/
MV_REG_BIT_RESET(MV_ETHCOMP_CTRL_REG(0), ETHCC_SW_FI_125_CLK_MASK);
MV_REG_BIT_SET(MV_ETHCOMP_CTRL_REG(0), (1 << ETHCC_SW_FI_125_CLK_OFFSET));
}
/* 3.1.3.2. Configure G-0 connection: set Regunit
* Ethernet_Complex_Control_0 register, field Gport0Source to
* "SwitchPort6" (0x1).
*/
reg = MV_REG_READ(MV_ETHCOMP_CTRL_REG(0));
if (ethCompCfg & ESC_OPT_MAC0_2_SW_P4) {
reg &= ~ETHCC_GPORT_0_SRC_MASK;
reg |= (0x1 << ETHCC_GPORT_0_SRC_OFFSET);
}
/* 3.2.3.2. Configure G-1 connection: set Regunit
* Ethernet_Complex_Control_0 register, field Gport1Source to
* SwitchPort5" (0x1).
*/
if (ethCompCfg & ESC_OPT_MAC1_2_SW_P5) {
reg &= ~ETHCC_GPORT_1_SRC_MASK;
reg |= (0x1 << ETHCC_GPORT_1_SRC_OFFSET);
}
MV_REG_WRITE(MV_ETHCOMP_CTRL_REG(0), reg);
/* 3.2.3.3. Configure Switch P5 connection: set Regunit
* Ethernet_Complex_Control_0 register, field SwitchPort5Source to
* "Gport1" (0x1).
*/
reg = MV_REG_READ(MV_ETHCOMP_CTRL_REG(0));
reg &= ~ETHCC_SW_PORT_5_SRC_MASK;
if (ethCompCfg & ESC_OPT_MAC1_2_SW_P5)
reg |= (0x1 << ETHCC_SW_PORT_5_SRC_OFFSET);
MV_REG_WRITE(MV_ETHCOMP_CTRL_REG(0), reg);
/* 3.1.4.2. Wait for Switch, Switch Global Status Register, field
* EEInt to be set to 0x1.
*/
mvOsDelay(100);
return MV_OK;
}
/*******************************************************************************
**
** onuEponSerdesPowerUpSeq
** ____________________________________________________________________________
**
** DESCRIPTION: The function set serdes
**
** PARAMETERS: None
**
** OUTPUTS: None
**
** RETURNS: MV_OK or error
**
*******************************************************************************/
MV_STATUS onuEponSerdesPowerUpSeq(void)
{
MV_STATUS status;
MV_U32 rxReady = 0;
MV_U32 txReady = 0;
MV_U32 initDone;
MV_U32 temp;
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_0_RST, 0x1, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_0_PU_Pll, 0x0, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_0_PU_RX, 0x0, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_0_PU_TX, 0x0, 0);
if (status != MV_OK)
return(status);
// asicOntMiscRegRead(mvAsicReg_PON_SERDES_PHY_CTRL_0, &temp, 0);
// temp &= ~(0x7);
// status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_0, temp, 0);
// if (status != MV_OK)
// return(status);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_0_SEL_GEPON, 0x1, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_0_REF_CLK_25M, 0x1, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_0_RST, 0x0, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
asicOntMiscRegRead(mvAsicReg_PON_SERDES_INTERNAL_PASSWORD, &temp, 0);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_INTERNAL_PASSWORD, temp | 0x76, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_INTERNAL_EN_LOOP_TIMING, 0x1, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_INTERNAL_PON_SELECT, 0x3, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
// status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_0_PU_Pll, 0x1, 0);
// if (status != MV_OK)
// return(status);
//
// mvOsDelay(40);
//
// status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_0_PU_RX, 0x1, 0);
// if (status != MV_OK)
// return(status);
//
// mvOsDelay(10);
//
// status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_0_PU_TX, 0x1, 0);
// if (status != MV_OK)
// return(status);
asicOntMiscRegRead(mvAsicReg_PON_SERDES_PHY_CTRL_0, &temp, 0);
temp |= (0x7);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_0, temp, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
temp = 0;
do
{
temp++;
status = asicOntMiscRegRead(mvAsicReg_PON_SERDES_PHY_CTRL_0_READY_TX, &txReady, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
status = asicOntMiscRegRead(mvAsicReg_PON_SERDES_PHY_CTRL_0_READY_RX, &rxReady, 0);
if (status != MV_OK)
return(status);
if ((temp % 10) == 0)
{
return (MV_FAIL);
}
} while ((txReady == 0) || (rxReady == 0));
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_0_RX_INIT, 0x1, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
temp = 0;
do
{
temp++;
status = asicOntMiscRegRead(mvAsicReg_PON_SERDES_PHY_CTRL_0_INIT_DONE, &initDone, 0);
if (status != MV_OK)
return(status);
if ((temp % 10) == 0)
{
return (MV_FAIL);
}
mvOsDelay(40);
} while (initDone == 0);
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_0_RX_INIT, 0x0, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
return(MV_OK);
}
MV_STATUS mvTdmInit(mv_tdm_params_t* tdmParams)
{
MV_U8 ch, sample;
MV_U32 pcmCtrlReg;
MV_TRC_REC("->%s\n",__FUNCTION__);
mvTdmShowProperties();
/* Init TDM windows address decoding */
if (mvTdmWinInit() != MV_OK)
{
return MV_ERROR;
}
/* Init globals */
rxInt = txInt = 0;
tdmEnable = 0;
spiMode = mvBoardTdmSpiModeGet();
tdmBandMode = tdmParams->bandMode;
pcmFormat = tdmParams->pcmFormat;
if((tdmParams->samplePeriod < MV_TDM_BASE_SAMPLE_PERIOD) ||
(tdmParams->samplePeriod > MV_TDM_MAX_SAMPLE_PERIOD))
{
factor = 1; /* use base sample period(10ms) */
}
else
{
factor = (tdmParams->samplePeriod / MV_TDM_BASE_SAMPLE_PERIOD);
}
/* Set sample size for further TDM configuration */
sample = (pcmFormat == MV_PCM_FORMAT_LINEAR ? 2 : 1);
/* Allocate aggregated buffers for data transport */
MV_TRC_REC("allocate %d bytes for aggregated buffer\n", MV_TDM_AGGR_BUFF_SIZE(pcmFormat, tdmBandMode, factor));
rxAggrBuffVirt = (MV_U8*)mvOsIoCachedMalloc(NULL, MV_TDM_AGGR_BUFF_SIZE(pcmFormat, tdmBandMode, factor),
&rxAggrBuffPhys,NULL);
txAggrBuffVirt = (MV_U8*)mvOsIoCachedMalloc(NULL, MV_TDM_AGGR_BUFF_SIZE(pcmFormat, tdmBandMode, factor),
&txAggrBuffPhys,NULL);
if(!rxAggrBuffVirt || !txAggrBuffVirt)
{
mvOsPrintf("%s: error malloc failed\n",__FUNCTION__);
return MV_NO_RESOURCE;
}
/* Config TDM */
MV_REG_BIT_RESET(TDM_SPI_MUX_REG, 1); /* enable TDM/SPI interface */
MV_REG_BIT_SET(TDM_MISC_REG, BIT0); /* sw reset to TDM for 5181L-A1 & up */
MV_REG_WRITE(INT_RESET_SELECT_REG,CLEAR_ON_ZERO); /* int cause is not clear on read */
MV_REG_WRITE(INT_EVENT_MASK_REG,0x3ffff); /* all interrupt bits latched in status */
MV_REG_WRITE(INT_STATUS_MASK_REG,0); /* disable interrupts */
MV_REG_WRITE(INT_STATUS_REG,0); /* clear int status register */
MV_REG_WRITE(PCM_CLK_RATE_DIV_REG, PCM_8192KHZ); /* PCM PCLK freq */
MV_REG_WRITE(DUMMY_RX_WRITE_DATA_REG,0); /* Padding on Rx completion */
MV_REG_BYTE_WRITE(SPI_GLOBAL_CTRL_REG, MV_REG_READ(SPI_GLOBAL_CTRL_REG) | SPI_GLOBAL_ENABLE);
MV_REG_BYTE_WRITE(SPI_CLK_PRESCALAR_REG, SPI_CLK_8MHZ); /* SPI SCLK freq */
MV_REG_WRITE(FRAME_TIMESLOT_REG, TIMESLOTS128_8192KHZ); /* Number of timeslots (PCLK) */
if(tdmBandMode == MV_NARROW_BAND)
{
pcmCtrlReg = (CONFIG_PCM_CRTL | ((sample-1)<<PCM_SAMPLE_SIZE_OFFS));
MV_REG_WRITE(PCM_CTRL_REG, pcmCtrlReg); /* PCM configuration */
MV_REG_WRITE(TIMESLOT_CTRL_REG, CONFIG_TIMESLOT_CTRL); /* channels rx/tx timeslots */
}
else /* MV_WIDE_BAND */
{
pcmCtrlReg = (CONFIG_WB_PCM_CRTL | ((sample-1)<<PCM_SAMPLE_SIZE_OFFS));
MV_REG_WRITE(PCM_CTRL_REG, pcmCtrlReg); /* PCM configuration - WB support */
MV_REG_WRITE(CH_DELAY_CTRL_REG(0), CONFIG_CH0_DELAY_CTRL_CONFIG); /* CH0 delay control register */
MV_REG_WRITE(CH_DELAY_CTRL_REG(1), CONFIG_CH1_DELAY_CTRL_CONFIG); /* CH1 delay control register */
MV_REG_WRITE(CH_WB_DELAY_CTRL_REG(0), CONFIG_CH0_WB_DELAY_CTRL_CONFIG); /* CH0 WB delay control register */
MV_REG_WRITE(CH_WB_DELAY_CTRL_REG(1), CONFIG_CH1_WB_DELAY_CTRL_CONFIG); /* CH1 WB delay control register */
}
/* Issue reset to codec(s) */
MV_TRC_REC("reseting voice unit(s)\n");
MV_REG_WRITE(MISC_CTRL_REG,0);
mvOsDelay(1);
MV_REG_WRITE(MISC_CTRL_REG,1);
if(spiMode)
{
/* Configure TDM to work in daisy chain mode */
mvTdmDaisyChainModeSet();
}
/* Initialize all HW units */
for(ch = 0 ; ch < MV_TDM_TOTAL_CHANNELS; ch++)
{
if(mvTdmChInit(ch) != MV_OK)
{
mvOsPrintf("mvTdmChInit(%d) failed !\n", ch);
return MV_ERROR;
}
}
/* Enable SLIC/DAA interrupt detection(before pcm is active) */
MV_REG_WRITE(INT_STATUS_MASK_REG, (MV_REG_READ(INT_STATUS_MASK_REG) | TDM_INT_SLIC));
MV_TRC_REC("<-%s\n",__FUNCTION__);
return MV_OK;
}
void kw_wol_configure(void)
{
MV_U16 phyAddr = mvBoardPhyAddrGet(WOL_PORT_NUM);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x16, 0x3);
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x12, 0x4905);
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x10, 0x181B);
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x16, 0x0);
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x0, 0x8000);
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x12, 0x80);
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x16, 0x11);
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x17, ((mvMacAddr[WOL_PORT_NUM][5] << 8) | (mvMacAddr[WOL_PORT_NUM][4])));
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x18, ((mvMacAddr[WOL_PORT_NUM][3] << 8) | (mvMacAddr[WOL_PORT_NUM][2])));
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x19, ((mvMacAddr[WOL_PORT_NUM][1] << 8) | (mvMacAddr[WOL_PORT_NUM][0])));
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x10, 0x4500);
mvOsDelay(10);
/* go to LED config page */
mvEthPhyRegWrite(phyAddr, 0x16, 0x3);
mvOsDelay(10);
/* configure SMI (system management interrupt) register */
MV_MEMIO_LE32_WRITE(MV_SYS_MANAG_INTERRUPT_REG, 0x02404185);
mvOsDelay(10);
}
/*******************************************************************************
* mvEth1145PhyInit - Initialize MARVELL 1145 Phy
*
* DESCRIPTION:
*
* INPUT:
* phyAddr - Phy address.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvEth1145PhyBasicInit(MV_U32 port)
{
MV_U16 value;
/* Set phy address for each port */
MV_REG_WRITE(ETH_PHY_ADDR_REG(port), mvBoardPhyAddrGet(port));
/* Set Link1000 output pin to be link indication, set Tx output pin to be activity */
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x18, ETH_PHY_LED_ACT_LNK_DV);
mvOsDelay(10);
/* Add delay to RGMII Tx and Rx */
mvEthPhyRegRead(mvBoardPhyAddrGet(port), 0x14, &value);
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x14,(value | BIT1 | BIT7));
mvOsDelay(10);
#if 0 /* Fix by yotam */
if (boardId != RD_78XX0_AMC_ID &&
boardId != RD_78XX0_H3C_ID) {
/* Set port 2 - Phy addr 9 to RGMII */
if (port == 2)
{
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x1b, 0x808b);
mvOsDelay(10);
}
/* Set port 1 - Phy addr a to SGMII */
if (port == 1)
{
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x1b, 0x8084);
mvOsDelay(10);
/* Reset Phy */
mvEthPhyRegRead( mvBoardPhyAddrGet(port), 0x00, &value);
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x00, (value | BIT15));
mvOsDelay(10);
#if defined(SGMII_OUTBAND_AN)
/* Set port 1 - Phy addr A Page 1 */
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x16, 0x1);
mvOsDelay(10);
/* Set port 1 - Phy addr A disable A.N. */
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x0, 0x140);
mvOsDelay(10);
/* Set port 1 - Phy addr A reset */
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x0, 0x8140);
mvOsDelay(10);
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x16, 0x0);
mvOsDelay(10);
#endif
}
}
#endif
/* Set Phy TPVL to 0 */
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x10, 0x60);
mvOsDelay(10);
/* Reset Phy */
mvEthPhyRegRead(mvBoardPhyAddrGet(port), 0x00, &value);
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x00, (value | BIT15));
mvOsDelay(10);
return;
}
MV_VOID mvEth1540A0PhyBasicInit(MV_BOOL eeeEnable)
{
int i;
MV_U16 reg;
int startAddr, endAddr;
startAddr = ethphyHalData.quadPhyStartAddr;
endAddr = startAddr + 4;
for (i = startAddr; i < endAddr; i++) {
/* Enable QSGMII AN */
/* Set page to 4. */
mvEthPhyRegWrite(i, 0x16, 4);
/* Enable AN */
mvEthPhyRegWrite(i, 0x0, 0x1140);
/* Set page to 0. */
mvEthPhyRegWrite(i, 0x16, 0);
/* Power up the phy */
mvEthPhyRegRead(i, ETH_PHY_CTRL_REG, ®);
reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
mvEthPhyRegWrite(i, ETH_PHY_CTRL_REG, reg);
/* Disable Drop BadTag */
mvEthPhyRegWrite(i, 22, 0x0010);
mvEthPhyRegWrite(i, 1, 0x000B);
mvEthPhyRegWrite(i, 2, 0x0000);
mvEthPhyRegWrite(i, 3, 0x0FB4);
mvEthPhyRegWrite(i, 1, 0x080B);
mvEthPhyRegWrite(i, 2, 0x0000);
mvEthPhyRegWrite(i, 3, 0x0FB4);
mvEthPhyRegWrite(i, 1, 0x100B);
mvEthPhyRegWrite(i, 2, 0x0000);
mvEthPhyRegWrite(i, 3, 0x0FB4);
mvEthPhyRegWrite(i, 1, 0x180B);
mvEthPhyRegWrite(i, 2, 0x0000);
mvEthPhyRegWrite(i, 3, 0x0FB4);
mvEthPhyRegWrite(i, 22, 0x0000);
mvEthPhyRegWrite(i, 22, 0x00FA);
mvEthPhyRegWrite(i, 8, 0x0010);
mvEthPhyRegWrite(i, 22, 0x00FB);
mvEthPhyRegWrite(i, 1, 0x4099);
mvEthPhyRegWrite(i, 3, 0x1120);
mvEthPhyRegWrite(i, 11, 0x113C);
mvEthPhyRegWrite(i, 14, 0x8100);
mvEthPhyRegWrite(i, 15, 0x112A);
mvEthPhyRegWrite(i, 22, 0x00FC);
mvEthPhyRegWrite(i, 1, 0x20B0);
mvEthPhyRegWrite(i, 22, 0x00FF);
mvEthPhyRegWrite(i, 17, 0x0000);
mvEthPhyRegWrite(i, 16, 0x2000);
mvEthPhyRegWrite(i, 17, 0x4444);
mvEthPhyRegWrite(i, 16, 0x2140);
mvEthPhyRegWrite(i, 17, 0x8064);
mvEthPhyRegWrite(i, 16, 0x2141);
mvEthPhyRegWrite(i, 17, 0x0108);
mvEthPhyRegWrite(i, 16, 0x2144);
mvEthPhyRegWrite(i, 17, 0x0F16);
mvEthPhyRegWrite(i, 16, 0x2146);
mvEthPhyRegWrite(i, 17, 0x8C44);
mvEthPhyRegWrite(i, 16, 0x214B);
mvEthPhyRegWrite(i, 17, 0x0F90);
mvEthPhyRegWrite(i, 16, 0x214C);
mvEthPhyRegWrite(i, 17, 0xBA33);
mvEthPhyRegWrite(i, 16, 0x214D);
mvEthPhyRegWrite(i, 17, 0x39AA);
mvEthPhyRegWrite(i, 16, 0x214F);
mvEthPhyRegWrite(i, 17, 0x8433);
mvEthPhyRegWrite(i, 16, 0x2151);
mvEthPhyRegWrite(i, 17, 0x2010);
mvEthPhyRegWrite(i, 16, 0x2152);
mvEthPhyRegWrite(i, 17, 0x99EB);
mvEthPhyRegWrite(i, 16, 0x2153);
mvEthPhyRegWrite(i, 17, 0x2F3B);
mvEthPhyRegWrite(i, 16, 0x2154);
mvEthPhyRegWrite(i, 17, 0x584E);
mvEthPhyRegWrite(i, 16, 0x2156);
mvEthPhyRegWrite(i, 17, 0x1223);
mvEthPhyRegWrite(i, 16, 0x2158);
mvEthPhyRegWrite(i, 22, 0x0000);
/* Enable EEE_Auto-neg for 1000BASE-T and 100BASE-TX */
mvEthPhyRegWrite(i, 22, 0x0000);
mvEthPhyRegWrite(i, 13, 0x0007);
mvEthPhyRegWrite(i, 14, 0x003C);
mvEthPhyRegWrite(i, 13, 0x4007);
mvEthPhyRegWrite(i, 14, 0x0006);
/* Enable MACSec (Reg 27_2.13 = '1') */
mvEthPhyRegWrite(i, 22, 0x0012);
mvEthPhyRegRead(i, 27, ®);
reg |= (1 << 13);
mvEthPhyRegWrite(i, 27, reg);
if (eeeEnable == MV_TRUE) {
/* Enable EEE Master (Legacy) Mode */
mvEthPhyRegWrite(i, 22, 0x0010);
mvEthPhyRegWrite(i, 1, 0x03c1);
mvEthPhyRegWrite(i, 2, 0x0001);
mvEthPhyRegWrite(i, 3, 0x0000);
mvEthPhyRegWrite(i, 1, 0x0bc1);
mvEthPhyRegWrite(i, 2, 0x0001);
mvEthPhyRegWrite(i, 3, 0x0000);
mvEthPhyRegWrite(i, 1, 0x13c1);
mvEthPhyRegWrite(i, 2, 0x0001);
mvEthPhyRegWrite(i, 3, 0x0000);
mvEthPhyRegWrite(i, 1, 0x1bc1);
mvEthPhyRegWrite(i, 2, 0x0001);
mvEthPhyRegWrite(i, 3, 0x0000);
mvEthPhyRegWrite(i, 22, 0x0000);
}
mvEthPhyRegWrite(i, 22, 0x0000);
mvEthPhyRegWrite(i, 0, 0x9140);
mvOsDelay(100);
}
// /* Sleep 3000 */
// mvOsDelay(300);
}
MV_VOID mvEth1540Y0PhyBasicInit(MV_BOOL eeeEnable)
{
int i;
MV_U16 reg;
int startAddr, endAddr;
startAddr = ethphyHalData.quadPhyStartAddr;
endAddr = startAddr + 4;
for (i = startAddr; i < endAddr; i++) {
/* Enable QSGMII AN */
/* Set page to 4. */
mvEthPhyRegWrite(i, 0x16, 4);
/* Enable AN */
mvEthPhyRegWrite(i, 0x0, 0x1140);
/* Set page to 0. */
mvEthPhyRegWrite(i, 0x16, 0);
/* Power up the phy */
mvEthPhyRegRead(i, ETH_PHY_CTRL_REG, ®);
reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
mvEthPhyRegWrite(i, ETH_PHY_CTRL_REG, reg);
mvOsDelay(100);
if (eeeEnable) {
/* set ELU#0 default match */
/* RW U1 P0 R22 H0010 */
mvEthPhyRegWrite(i, 0x16, 0x10);
/* RW U1 P0 R1 H0104 */
mvEthPhyRegWrite(i, 0x1, 0x0104);
/* RW U1 P0 R2 h0000 */
mvEthPhyRegWrite(i, 0x2, 0x0000);
/* RW U1 P0 R3 H4000 */
mvEthPhyRegWrite(i, 0x3, 0x4000);
/* RW U1 P0 R1 H0904 */
mvEthPhyRegWrite(i, 0x1, 0x0904);
/* RW U1 P0 R2 h0000 */
mvEthPhyRegWrite(i, 0x2, 0x0000);
/* RW U1 P0 R3 H4000 */
mvEthPhyRegWrite(i, 0x3, 0x4000);
/* RW U1 P0 R1 H1104 */
mvEthPhyRegWrite(i, 0x1, 0x1104);
/* RW U1 P0 R2 h0000 */
mvEthPhyRegWrite(i, 0x2, 0x0000);
/* RW U1 P0 R3 H4000 */
mvEthPhyRegWrite(i, 0x3, 0x4000);
/* RW U1 P0 R1 H1904 */
mvEthPhyRegWrite(i, 0x1, 0x1904);
/* RW U1 P0 R2 h0000 */
mvEthPhyRegWrite(i, 0x2, 0x0000);
/* RW U1 P0 R3 H4000 */
mvEthPhyRegWrite(i, 0x3, 0x4000);
/* RW U1 P0 R22 H0000 */
mvEthPhyRegWrite(i, 0x16, 0x0000);
/* set ILU#0 default match */
/* RW U1 P0 R22 H0010 */
mvEthPhyRegWrite(i, 0x16, 0x0010);
/* RW U1 P0 R1 H0207 */
mvEthPhyRegWrite(i, 0x1, 0x0207);
/* RW U1 P0 R2 h4000 */
mvEthPhyRegWrite(i, 0x2, 0x4000);
/* RW U1 P0 R3 H0000 */
mvEthPhyRegWrite(i, 0x3, 0x0000);
/* RW U1 P0 R1 H0A07 */
mvEthPhyRegWrite(i, 0x1, 0x0a07);
/* RW U1 P0 R2 h4000 */
mvEthPhyRegWrite(i, 0x2, 0x4000);
/* RW U1 P0 R3 H0000 */
mvEthPhyRegWrite(i, 0x3, 0x0000);
/* RW U1 P0 R1 H1207 */
mvEthPhyRegWrite(i, 0x1, 0x1207);
/* RW U1 P0 R2 h4000 */
mvEthPhyRegWrite(i, 0x2, 0x4000);
/* RW U1 P0 R3 H0000 */
mvEthPhyRegWrite(i, 0x3, 0x0000);
/* RW U1 P0 R1 H1A07 */
mvEthPhyRegWrite(i, 0x1, 0x1a07);
/* RW U1 P0 R2 h4000 */
mvEthPhyRegWrite(i, 0x2, 0x4000);
/* RW U1 P0 R3 H0000 */
mvEthPhyRegWrite(i, 0x3, 0x0000);
/* RW U1 P0 R22 H0000 */
mvEthPhyRegWrite(i, 0x16, 0x0000);
/* change the wiremac ipg from 12 to 11 */
/* RW U1 P0 R22 H0010 */
mvEthPhyRegWrite(i, 0x16, 0x0010);
/* RW U1 P0 R1 H0041 */
mvEthPhyRegWrite(i, 0x1, 0x0041);
/* RW U1 P0 R2 h00b1 */
mvEthPhyRegWrite(i, 0x2, 0x00b1);
/* RW U1 P0 R3 H0002 */
mvEthPhyRegWrite(i, 0x3, 0x0002);
/* RW U1 P0 R1 H0841 */
mvEthPhyRegWrite(i, 0x1, 0x0841);
/* RW U1 P0 R2 h00b1 */
mvEthPhyRegWrite(i, 0x2, 0x00b1);
/* RW U1 P0 R3 H0002 */
mvEthPhyRegWrite(i, 0x3, 0x0002);
/* RW U1 P0 R1 H1041 */
mvEthPhyRegWrite(i, 0x1, 0x1041);
/* RW U1 P0 R2 h00b1 */
mvEthPhyRegWrite(i, 0x2, 0x00b1);
/* RW U1 P0 R3 H0002 */
mvEthPhyRegWrite(i, 0x3, 0x0002);
/* RW U1 P0 R1 H1841 */
mvEthPhyRegWrite(i, 0x1, 0x1841);
/* RW U1 P0 R2 h00b1 */
mvEthPhyRegWrite(i, 0x2, 0x00b1);
/* RW U1 P0 R3 H0002 */
mvEthPhyRegWrite(i, 0x3, 0x0002);
/* RW U1 P0 R22 H0000 */
mvEthPhyRegWrite(i, 0x16, 0x0000);
/* change the setting to not drop badtag */
/* RW U1 P0 R22 H0010 */
mvEthPhyRegWrite(i, 0x16, 0x0010);
/* RW U1 P0 R1 H000b */
mvEthPhyRegWrite(i, 0x1, 0x000b);
/* RW U1 P0 R2 h0000 */
mvEthPhyRegWrite(i, 0x2, 0x0000);
/* RW U1 P0 R3 H0fb4 */
mvEthPhyRegWrite(i, 0x3, 0x0fb4);
/* RW U1 P0 R1 H080b */
mvEthPhyRegWrite(i, 0x1, 0x080b);
/* RW U1 P0 R2 h0000 */
mvEthPhyRegWrite(i, 0x2, 0x0000);
/* RW U1 P0 R3 H0fb4 */
mvEthPhyRegWrite(i, 0x3, 0x0fb4);
/* RW U1 P0 R1 H100b */
mvEthPhyRegWrite(i, 0x1, 0x100b);
/* RW U1 P0 R2 h0000 */
mvEthPhyRegWrite(i, 0x2, 0x0000);
/* RW U1 P0 R3 H0fb4 */
mvEthPhyRegWrite(i, 0x3, 0x0fb4);
/* RW U1 P0 R1 H180b */
mvEthPhyRegWrite(i, 0x1, 0x180b);
/* RW U1 P0 R2 h0000 */
mvEthPhyRegWrite(i, 0x2, 0x0000);
/* RW U1 P0 R3 H0fb4 */
mvEthPhyRegWrite(i, 0x3, 0x0fb4);
/* RW U1 P0 R22 H0000 */
mvEthPhyRegWrite(i, 0x16, 0x0000);
/* set MACSec EEE Entry/Exit Timer */
/* RW U1 P0 R22 H0010 */
mvEthPhyRegWrite(i, 0x16, 0x0010);
/* RW U1 P0 R1 H03C0 */
mvEthPhyRegWrite(i, 0x1, 0x03c0);
/* RW U1 P0 R2 H111E */
mvEthPhyRegWrite(i, 0x2, 0x111e);
/* RW U1 P0 R3 H111E */
mvEthPhyRegWrite(i, 0x3, 0x111e);
/* RW U1 P0 R1 H0BC0 */
mvEthPhyRegWrite(i, 0x1, 0x0bc0);
/* RW U1 P0 R2 H111E */
mvEthPhyRegWrite(i, 0x2, 0x111e);
/* RW U1 P0 R3 H111E */
mvEthPhyRegWrite(i, 0x3, 0x111e);
/* RW U1 P0 R1 H13C0 */
mvEthPhyRegWrite(i, 0x1, 0x13c0);
/* RW U1 P0 R2 H111E */
mvEthPhyRegWrite(i, 0x2, 0x111e);
/* RW U1 P0 R3 H111E */
mvEthPhyRegWrite(i, 0x3, 0x111e);
/* RW U1 P0 R1 H1BC0 */
mvEthPhyRegWrite(i, 0x1, 0x1bc0);
/* RW U1 P0 R2 H111E */
mvEthPhyRegWrite(i, 0x2, 0x111e);
/* RW U1 P0 R3 H111E */
mvEthPhyRegWrite(i, 0x3, 0x111e);
/* RW U1 P0 R22 H0000 */
mvEthPhyRegWrite(i, 0x16, 0x0000);
/* Start of EEE Workaround */
/* RW U1 P0-3 R22 H00FB */
mvEthPhyRegWrite(i, 0x16, 0x00FB);
/* RW U1 P0-3 R11 H1120 */
mvEthPhyRegWrite(i, 0xB , 0x1120);
/* RW U1 P0-3 R8 H3666 */
mvEthPhyRegWrite(i, 0x8 , 0x3666);
/* RW U1 P0-3 R22 H00FF */
mvEthPhyRegWrite(i, 0x16, 0x00FF);
/* RW U1 P0-3 R17 H0F0C */
mvEthPhyRegWrite(i, 0x11, 0x0F0C);
/* RW U1 P0-3 R16 H2146 */
mvEthPhyRegWrite(i, 0x10, 0x2146);
/* RW U1 P0-3 R17 Hc090 */
mvEthPhyRegWrite(i, 0x11, 0xC090);
/* RW U1 P0-3 R16 H2147 */
mvEthPhyRegWrite(i, 0x10, 0x2147);
/* RW U1 P0-3 R17 H0000 */
mvEthPhyRegWrite(i, 0x11, 0x0000);
/* RW U1 P0-3 R16 H2000 */
mvEthPhyRegWrite(i, 0x10, 0x2000);
/* RW U1 P0-3 R17 H6000 */
mvEthPhyRegWrite(i, 0x11, 0x6000);
/* RW U1 P0-3 R16 H2143 */
mvEthPhyRegWrite(i, 0x10, 0x2143);
/* RW U1 P0-3 R17 HC004 */
mvEthPhyRegWrite(i, 0x11, 0xC004);
/* RW U1 P0-3 R16 H2100 */
mvEthPhyRegWrite(i, 0x10, 0x2100);
/* RW U1 P0-3 R17 H49E8 */
mvEthPhyRegWrite(i, 0x11, 0x49E8);
/* RW U1 P0-3 R16 H2144 */
mvEthPhyRegWrite(i, 0x10, 0x2144);
/* RW U1 P0-3 R17 H3180 */
mvEthPhyRegWrite(i, 0x11, 0x3180);
/* RW U1 P0-3 R16 H2148 */
mvEthPhyRegWrite(i, 0x10, 0x2148);
/* RW U1 P0-3 R17 HFC44 */
mvEthPhyRegWrite(i, 0x11, 0xFC44);
/* RW U1 P0-3 R16 H214B */
mvEthPhyRegWrite(i, 0x10, 0x214B);
/* RW U1 P0-3 R17 H7FD2 */
mvEthPhyRegWrite(i, 0x11, 0x7FD2);
/* RW U1 P0-3 R16 H214C */
mvEthPhyRegWrite(i, 0x10, 0x214C);
/* RW U1 P0-3 R17 H2240 */
mvEthPhyRegWrite(i, 0x11, 0x2240);
/* RW U1 P0-3 R16 H214D */
mvEthPhyRegWrite(i, 0x10, 0x214D);
/* RW U1 P0-3 R17 H3008 */
mvEthPhyRegWrite(i, 0x11, 0x3008);
/* RW U1 P0-3 R16 H214E */
mvEthPhyRegWrite(i, 0x10, 0x214E);
/* RW U1 P0-3 R17 H3DF0 */
mvEthPhyRegWrite(i, 0x11, 0x3DF0);
/* RW U1 P0-3 R16 H214F */
mvEthPhyRegWrite(i, 0x10, 0x214F);
/* RW U1 P0-3 R22 H0000 */
mvEthPhyRegWrite(i, 0x16, 0);
/* Enable EEE Auto-neg advertisement on P0-P7 ports */
/* RW U1 P0-3 R13 H0007 */
mvEthPhyRegWrite(i, 0xD , 0x0007);
/* RW U1 P0-3 R14 H003C */
mvEthPhyRegWrite(i, 0xE , 0x003C);
/* RW U1 P0-3 R13 H4007 */
mvEthPhyRegWrite(i, 0xD , 0x4007);
/* RW U1 P0-3 R14 H0006 */
mvEthPhyRegWrite(i, 0xE , 0x0006);
/* Soft-Reset on P0-P7 ports */
/* RW U1 P0-3 R22 H0000 */
mvEthPhyRegWrite(i, 0x16, 0);
/* RW U1 P0-3 R0 H9140 */
mvEthPhyRegWrite(i, 0x0 , 0x9140);
/* Enable MACsec EEE Master Mode on P0-3 ports */
/* RW U1 P0 R22 H0010 */
mvEthPhyRegWrite(i, 0x16, 0x0010);
/* RW U1 P0 R1 H03C1 */
mvEthPhyRegWrite(i, 0x1 , 0x03C1);
/* RW U1 P0 R2 H0001 */
mvEthPhyRegWrite(i, 0x2 , 0x0001);
/* RW U1 P0 R3 H0000 */
mvEthPhyRegWrite(i, 0x3 , 0x0000);
/* RW U1 P0 R1 H0BC1 */
mvEthPhyRegWrite(i, 0x1 , 0x0BC1);
/* RW U1 P0 R2 H0001 */
mvEthPhyRegWrite(i, 0x2 , 0x0001);
/* RW U1 P0 R3 H0000 */
mvEthPhyRegWrite(i, 0x3 , 0x0000);
/* RW U1 P0 R1 H13C1 */
mvEthPhyRegWrite(i, 0x1 , 0x13C1);
/* RW U1 P0 R2 H0001 */
mvEthPhyRegWrite(i, 0x2 , 0x0001);
/* RW U1 P0 R3 H0000 */
mvEthPhyRegWrite(i, 0x3 , 0x0000);
/* RW U1 P0 R1 H1BC1 */
mvEthPhyRegWrite(i, 0x1 , 0x1BC1);
/* RW U1 P0 R2 H0001 */
mvEthPhyRegWrite(i, 0x2 , 0x0001);
/* RW U1 P0 R3 H0000 */
mvEthPhyRegWrite(i, 0x3 , 0x0000);
/* RW U1 P0 R22 H0000 */
mvEthPhyRegWrite(i, 0x16, 0x0000);
}
/* set ELU#0 default match */
/* RW U1 P0 R22 H0010 */
/* RW U1 P0 R1 H0104 */
/* RW U1 P0 R2 h0000 */
/* RW U1 P0 R3 H4000 */
/* RW U1 P0 R1 H0904 */
/* RW U1 P0 R2 h0000 */
/* RW U1 P0 R3 H4000 */
/* RW U1 P0 R1 H1104 */
/* RW U1 P0 R2 h0000 */
/* RW U1 P0 R3 H4000 */
/* RW U1 P0 R1 H1904 */
/* RW U1 P0 R2 h0000 */
/* RW U1 P0 R3 H4000 */
/* RW U1 P0 R22 H0000 */
mvEthPhyRegWrite(i, 0x16, 0x0000);
/* set ILU#0 default match */
/* RW U1 P0 R22 H0010 */
mvEthPhyRegWrite(i, 0x16, 0x0010);
/* RW U1 P0 R1 H0207 */
/* RW U1 P0 R2 h4000 */
/* RW U1 P0 R3 H0000 */
/* RW U1 P0 R1 H0A07 */
/* RW U1 P0 R2 h4000 */
/* RW U1 P0 R3 H0000 */
/* RW U1 P0 R1 H1207 */
/* RW U1 P0 R2 h4000 */
/* RW U1 P0 R3 H0000 */
/* RW U1 P0 R1 H1A07 */
/* RW U1 P0 R2 h4000 */
/* RW U1 P0 R3 H0000 */
/* RW U1 P0 R22 H0000 */
mvEthPhyRegWrite(i, 0x16, 0x0000);
/* change the wiremac ipg from 12 to 11 */
/* RW U1 P0 R22 H0010 */
mvEthPhyRegWrite(i, 0x16, 0x0010);
/* RW U1 P0 R1 H0041 */
/* RW U1 P0 R2 h00b1 */
/* RW U1 P0 R3 H0002 */
/* RW U1 P0 R1 H0841 */
/* RW U1 P0 R2 h00b1 */
/* RW U1 P0 R3 H0002 */
/* RW U1 P0 R1 H1041 */
/* RW U1 P0 R2 h00b1 */
/* RW U1 P0 R3 H0002 */
/* RW U1 P0 R1 H1841 */
/* RW U1 P0 R2 h00b1 */
/* RW U1 P0 R3 H0002 */
/* RW U1 P0 R22 H0000 */
mvEthPhyRegWrite(i, 0x16, 0x0000);
/* change the setting to not drop badtag */
/* RW U1 P0 R22 H0010 */
mvEthPhyRegWrite(i, 0x16, 0x0010);
/* RW U1 P0 R1 H000b */
/* RW U1 P0 R2 h0000 */
/* RW U1 P0 R3 H0fb4 */
/* RW U1 P0 R1 H080b */
/* RW U1 P0 R2 h0000 */
/* RW U1 P0 R3 H0fb4 */
/* RW U1 P0 R1 H100b */
/* RW U1 P0 R2 h0000 */
/* RW U1 P0 R3 H0fb4 */
/* RW U1 P0 R1 H180b */
/* RW U1 P0 R2 h0000 */
/* RW U1 P0 R3 H0fb4 */
/* RW U1 P0 R22 H0000 */
mvEthPhyRegWrite(i, 0x16, 0x0000);
/* set MACSec EEE Entry/Exit Timer */
/* RW U1 P0 R22 H0010 */
mvEthPhyRegWrite(i, 0x16, 0x0010);
/* RW U1 P0 R1 H03C0 */
/* RW U1 P0 R2 H111E */
/* RW U1 P0 R3 H111E */
/* RW U1 P0 R1 H0BC0 */
/* RW U1 P0 R2 H111E */
/* RW U1 P0 R3 H111E */
/* RW U1 P0 R1 H13C0 */
/* RW U1 P0 R2 H111E */
/* RW U1 P0 R3 H111E */
/* RW U1 P0 R1 H1BC0 */
/* RW U1 P0 R2 H111E */
/* RW U1 P0 R3 H111E */
/* RW U1 P0 R22 H0000 */
/* RW U1 P0-3 R22 H00FB */
/* RW U1 P0-3 R11 H1120 */
/* RW U1 P0-3 R8 H3666 */
/* RW U1 P0-3 R22 H00FF */
/* RW U1 P0-3 R17 H0F0C */
/* RW U1 P0-3 R16 H2146 */
/* RW U1 P0-3 R17 Hc090 */
/* RW U1 P0-3 R16 H2147 */
/* RW U1 P0-3 R17 H0000 */
/* RW U1 P0-3 R16 H2000 */
/* RW U1 P0-3 R17 H6000 */
/* RW U1 P0-3 R16 H2143 */
/* RW U1 P0-3 R17 HC004 */
/* RW U1 P0-3 R16 H2100 */
/* RW U1 P0-3 R17 H49E8 */
/* RW U1 P0-3 R16 H2144 */
/* RW U1 P0-3 R17 H3180 */
/* RW U1 P0-3 R16 H2148 */
/* RW U1 P0-3 R17 HFC44 */
/* RW U1 P0-3 R16 H214B */
/* RW U1 P0-3 R17 H7FD2 */
/* RW U1 P0-3 R16 H214C */
/* RW U1 P0-3 R17 H2240 */
/* RW U1 P0-3 R16 H214D */
/* RW U1 P0-3 R17 H3008 */
/* RW U1 P0-3 R16 H214E */
/* RW U1 P0-3 R17 H3DF0 */
/* RW U1 P0-3 R16 H214F */
/* RW U1 P0-3 R22 H0000 */
/* RW U1 P0-3 R13 H0007 */
/* RW U1 P0-3 R14 H003C */
/* RW U1 P0-3 R13 H4007 */
/* RW U1 P0-3 R14 H0006 */
/* RW U1 P0-3 R22 H0000 */
/* RW U1 P0-3 R0 H9140 */
/* RW U1 P0 R22 H0010 */
/* RW U1 P0 R1 H03C1 */
/* RW U1 P0 R2 H0001 */
/* RW U1 P0 R3 H0000 */
/* RW U1 P0 R1 H0BC1 */
/* RW U1 P0 R2 H0001 */
/* RW U1 P0 R3 H0000 */
/* RW U1 P0 R1 H13C1 */
/* RW U1 P0 R2 H0001 */
/* RW U1 P0 R3 H0000 */
/* RW U1 P0 R1 H1BC1 */
/* RW U1 P0 R2 H0001 */
/* RW U1 P0 R3 H0000 */
/* RW U1 P0 R22 H0000 */
mvEthPhyRegWrite(i, 0x16, 0x0000);
if (eeeEnable == MV_FALSE) {
/* Disable MACSec */
mvEthPhyRegWrite(i, 0x16, 0x12);
mvEthPhyRegRead(i, 27, ®);
reg &= ~(1 << 13);
mvEthPhyRegWrite(i, 27, reg);
}
mvEthPhyRegWrite(i, 0x16, 0x0000);
}
/* Sleep 3000 */
mvOsDelay(300);
}
/*******************************************************************************
* mvCtrlHighSpeedSerdesPhyConfig
*
* DESCRIPTION: This is the main function which configure the
* PU sequence of the ser-des
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_OK - success
* MV_ERROR - failure
*******************************************************************************/
MV_STATUS mvCtrlHighSpeedSerdesPhyConfig(MV_VOID)
{
MV_U32 serdesLaneNum, pexUnit;
MV_U32 uiReg;
MV_BIN_SERDES_UNIT_INDX serdesLaneCfg;
MV_U32 regAddr[16][11], regVal[16][11]; /* addr/value for each line @ every setup step */
MV_U8 maxSerdesLanes;
MV_U32 tmp;
MV_U32 tempReg, tempPexReg;
MV_U32 pexIf=0;
MV_U32 first_busno, next_busno;
MV_U32 addr;
MV_TWSI_ADDR slave;
MV_U32 boardId = mvBoardIdIndexGet(mvBoardIdGet());
maxSerdesLanes = mvCtrlSerdesMaxLanesGet();
if (maxSerdesLanes == 0)
return MV_OK;
/*Set MPP1 for twsi access */
uiReg = (MV_REG_READ(MPP_CONTROL_REG(1)) & 0x00FFFFFF) | 0x22000000;
MV_REG_WRITE(MPP_CONTROL_REG(1), uiReg);
/* TWSI init */
slave.type = ADDR7_BIT;
slave.address = 0;
mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0);
mvUartInit();
/* update board configuration (serdes lane topology and speed), if needed */
mvBoardUpdateBoardTopologyConfig(boardId);
/* Initialize board configuration database */
boardLaneConfig[0] = SERDES_UNIT_PEX; /* SerDes 0 is alwyas PCIe0*/
boardLaneConfig[1] = boardTopologyConfig[boardId].serdesTopology.lane1;
boardLaneConfig[2] = boardTopologyConfig[boardId].serdesTopology.lane2;
boardLaneConfig[3] = boardTopologyConfig[boardId].serdesTopology.lane3;
memset(regAddr, 0, sizeof(regAddr));
memset(regVal, 0, sizeof(regVal));
/* Check if DRAM is already initialized */
if (MV_REG_READ(REG_BOOTROM_ROUTINE_ADDR) & (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
DEBUG_INIT_S("High speed PHY - Version: ");
DEBUG_INIT_S(SERDES_VERION);
DEBUG_INIT_S(" - 2nd boot - Skip \n");
return MV_OK;
}
DEBUG_INIT_S("High speed PHY - Version: ");
DEBUG_INIT_S(SERDES_VERION);
DEBUG_INIT_S(" (COM-PHY-V20) \n");
DEBUG_INIT_FULL_C("SERDES 0=",boardLaneConfig[0],2);
DEBUG_INIT_FULL_C("SERDES 1=",boardLaneConfig[1],2);
DEBUG_INIT_FULL_C("SERDES 2=",boardLaneConfig[2],2);
DEBUG_INIT_FULL_C("SERDES 3=",boardLaneConfig[3],2);
/*------------------------------------------*/
/* STEP - 1.5 Power Down PLL, RX, TX all phys */
/*------------------------------------------*/
for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++)
{
uiReg=MV_REG_READ(COMMON_PHY_CONFIGURATION1_REG(serdesLaneNum));
uiReg &= ~PIN_TX_IDLE_MASK;
uiReg &= ~(PHY_POWER_UP_PLL_MASK | PHY_POWER_UP_RX_MASK | PHY_POWER_UP_TX_MASK);
MV_REG_WRITE(COMMON_PHY_CONFIGURATION1_REG(serdesLaneNum),uiReg);
}
mvOsUDelay(10000);
/*--------------------------------------------------------*/
/* STEP - 2 Reset PHY and PIPE (Zx: Un-reset, Ax: Reset)*/
/*--------------------------------------------------------*/
for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++)
{
#ifndef CONFIG_ALP_A375_ZX_REV
resetPhyAndPipe(serdesLaneNum, MV_TRUE);
#else
resetPhyAndPipe(serdesLaneNum, MV_FALSE);
#endif
}
/*--------------------------------*/
/* STEP - 2 Common PHYs Selectors */
/*--------------------------------*/
MV_REG_WRITE(COMMON_PHY_SELECTOR_REG, GetLaneSelectorConfig());
/*--------------------------------*/
/* STEP - 3 Configuration 1 */
/*--------------------------------*/
for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++) {
serdesLaneCfg = mvGetSerdesLaneCfg(serdesLaneNum);
if(serdesLaneCfg >= SERDES_LAST_UNIT){
return MV_ERROR;
}
uiReg = MV_REG_READ(COMMON_PHY_CONFIGURATION1_REG(serdesLaneNum));
switch(serdesLaneCfg){
case SERDES_UNIT_USB3:
#ifndef CONFIG_ALP_A375_ZX_REV
A375_A0_COMMON_PHY_CONFIG(uiReg);
#endif
uiReg |= PHY_MODE_MASK; /* PHY Mode = USB */
uiReg |= PIPE_SELECT_MASK ; /* Select USB3_PEX */
break;
case SERDES_UNIT_PEX:
uiReg |= PIPE_SELECT_MASK ; /* Select USB3_PEX */
#ifndef CONFIG_ALP_A375_ZX_REV
uiReg &= ~(PHY_MODE_MASK); /* PHY Mode = PEX */
A375_A0_COMMON_PHY_CONFIG(uiReg);
#endif
break;
case SERDES_UNIT_SGMII:
case SERDES_UNIT_SATA:
#ifndef CONFIG_ALP_A375_ZX_REV
A375_A0_COMMON_PHY_CONFIG(uiReg);
#endif
uiReg &= ~(PIPE_SELECT_MASK); /* Select SATA_SGMII */
uiReg |= POWER_UP_IVREF_MASK; /* Power UP IVREF = Power Up */
break;
case SERDES_UNIT_UNCONNECTED:
default:
break;
}
/* Serdes speed config */
tmp = getSerdesSpeedConfig(boardId, serdesLaneCfg);
uiReg &= ~(GEN_RX_MASK); /* SERDES RX Speed config */
uiReg |= tmp<<GEN_RX_OFFS;
uiReg &= ~(GEN_TX_MASK); /* SERDES TX Speed config */
uiReg |= tmp<<GEN_TX_OFFS;
MV_REG_WRITE(COMMON_PHY_CONFIGURATION1_REG(serdesLaneNum),uiReg);
}
#ifndef CONFIG_ALP_A375_ZX_REV
/*------------------------------------------*/
/* STEP - 3.5 Unreset PHY and PIPE(only Ax)*/
/*------------------------------------------*/
for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++) {
resetPhyAndPipe(serdesLaneNum, MV_FALSE);
}
#endif
/*----------------------------------------*/
/* STEP - 4 COMPHY register configuration */
/*----------------------------------------*/
for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++) {
serdesLaneCfg = mvGetSerdesLaneCfg(serdesLaneNum);
if(serdesLaneCfg >= SERDES_LAST_UNIT){
return MV_ERROR;
}
switch(serdesLaneCfg){
case SERDES_UNIT_PEX:
MV_REG_WRITE(RESET_AND_CLOCK_CONTROL_REG(serdesLaneNum),0x25); /* Enable soft_reset*/
MV_REG_WRITE(POWER_AND_PLL_CONTROL_REG(serdesLaneNum),0xFC60); /* PHY Mode = PEX */
#ifndef CONFIG_ALP_A375_ZX_REV
MV_REG_WRITE(MISCELLANEOUS_CONTROL0_REG(serdesLaneNum),0x6017); /* REFCLK SEL =0x0 (100Mhz) */
MV_REG_WRITE(INTERFACE_REG1_REG(serdesLaneNum),0x1400); /* PHY_Gen_Max = 5G */
MV_REG_WRITE(DIGITAL_LOOPBACK_ENABLE_REG(serdesLaneNum),0x400); /* SEL_Bits = 20-Bit */
A375_A0_RESET_DFE_SEQUENCE(serdesLaneNum);
#else
MV_REG_WRITE(KVCO_CALOBRATION_CONTROL_REG(serdesLaneNum),0x40); /* use_max_pll_rate=0x0, ext_force_cal_done=0x0 */
#endif
MV_REG_WRITE(RESET_AND_CLOCK_CONTROL_REG(serdesLaneNum),0x24); /* Release soft_reset */
break;
case SERDES_UNIT_USB3:
MV_REG_WRITE(RESET_AND_CLOCK_CONTROL_REG(serdesLaneNum),0x21); /* Enable soft_reset*/
MV_REG_WRITE(POWER_AND_PLL_CONTROL_REG(serdesLaneNum),0xFCA0); /* PHY Mode = USB3 */
#ifndef CONFIG_ALP_A375_ZX_REV
MV_REG_WRITE(LANE_CONFIGURATION_4_REG(serdesLaneNum),0x13); /* Ref_Clk =100Mhz */
MV_REG_WRITE(MISCELLANEOUS_CONTROL0_REG(serdesLaneNum),0x6017); /* REFCLK SEL =0x0 (100Mhz) */
MV_REG_WRITE(INTERFACE_REG1_REG(serdesLaneNum),0x1400); /* PHY_Gen_Max = 5G */
MV_REG_WRITE(DIGITAL_LOOPBACK_ENABLE_REG(serdesLaneNum),0x400); /* SEL_Bits = 20-Bit */
A375_A0_RESET_DFE_SEQUENCE(serdesLaneNum);
#else
MV_REG_WRITE(KVCO_CALOBRATION_CONTROL_REG(serdesLaneNum),0x40); /* use_max_pll_rate=0x0, ext_force_cal_done=0x0 */
MV_REG_WRITE(GENERETION_2_SETTINGS_1_REG(serdesLaneNum),0x149); /* Mulitiple frequency setup */
#endif
MV_REG_WRITE(RESET_AND_CLOCK_CONTROL_REG(serdesLaneNum),0x20); /* Release soft_reset */
break;
case SERDES_UNIT_SATA:
MV_REG_WRITE(POWER_AND_PLL_CONTROL_REG(serdesLaneNum),0xFC01); /* PHY Mode = SATA */
MV_REG_WRITE(MISCELLANEOUS_CONTROL0_REG(serdesLaneNum),0x6417); /* REFCLK SEL =0x1 (25Mhz) */
#ifndef CONFIG_ALP_A375_ZX_REV
MV_REG_WRITE(INTERFACE_REG1_REG(serdesLaneNum),0x1400); /* PHY_Gen_Max = 5G */
MV_REG_WRITE(DIGITAL_LOOPBACK_ENABLE_REG(serdesLaneNum),0x400); /* SEL_Bits = 20-Bit */
MV_REG_WRITE(DIGITAL_RESERVED0_REG(serdesLaneNum),0xE); /* Reg_sq_de_glitch_en */
A375_A0_RESET_DFE_SEQUENCE(serdesLaneNum);
#else
MV_REG_WRITE(RESERVED_46_REG(serdesLaneNum),0xFF00);
#endif
break;
case SERDES_UNIT_SGMII:
MV_REG_WRITE(POWER_AND_PLL_CONTROL_REG(serdesLaneNum),0xFC81); /* PHY Mode = SGMII */ /*moti need to change offset*/
MV_REG_WRITE(DIGITAL_LOOPBACK_ENABLE_REG(serdesLaneNum),0x0); /* SEL_BITS = 0x0 (10-bits mode) */
MV_REG_WRITE(MISCELLANEOUS_CONTROL0_REG(serdesLaneNum),0x6417); /* REFCLK SEL =0x1 (25Mhz) */
#ifndef CONFIG_ALP_A375_ZX_REV
MV_REG_WRITE(DIGITAL_RESERVED0_REG(serdesLaneNum),0xE); /* Reg_sq_de_glitch_en */
A375_A0_RESET_DFE_SEQUENCE(serdesLaneNum);
#else
MV_REG_WRITE(RESERVED_46_REG(serdesLaneNum),0xFF00); /* Enable soft_reset*/
#endif
MV_REG_WRITE(PHY_ISOLATION_MODE_CONTROL_REG(serdesLaneNum),0x166); /* Set PHY_GEN_TX/RX to 1.25Gbps */
break;
case SERDES_UNIT_UNCONNECTED:
default:
break;
}
}
/*------------------------------------------*/
/* STEP - 4.5 Power up PLL, RX, TX all phys */
/*------------------------------------------*/
for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++)
{
uiReg=MV_REG_READ(COMMON_PHY_CONFIGURATION1_REG(serdesLaneNum));
uiReg |= (PHY_POWER_UP_PLL_MASK | PHY_POWER_UP_RX_MASK | PHY_POWER_UP_TX_MASK);
MV_REG_WRITE(COMMON_PHY_CONFIGURATION1_REG(serdesLaneNum),uiReg);
}
#ifndef CONFIG_ALP_A375_ZX_REV
mvOsUDelay(5000);
/*--------------------------------------------------------------------*/
/* STEP - 4.6 (Only SGMII/SATA): WAIT for PHY Power up sequence to finish */
/*--------------------------------------------------------------------*/
for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++) {
serdesLaneCfg = mvGetSerdesLaneCfg(serdesLaneNum);
if(serdesLaneCfg >= SERDES_LAST_UNIT){
return MV_ERROR;
}
switch(serdesLaneCfg){
case SERDES_UNIT_SATA:
case SERDES_UNIT_SGMII:
uiReg = MV_REG_READ(COMMON_PHY_STATUS1_REG(serdesLaneNum));
if ((uiReg & 0x6) != 0x6) {
DEBUG_INIT_S("Phy Power up did't finished\n");
return MV_ERROR;
}
case SERDES_UNIT_UNCONNECTED:
default:
break;
}
}
#endif
/*----------------------------------------*/
/* STEP - 5 PEX Only */
/*----------------------------------------*/
for (pexUnit = 0; pexUnit < 4; pexUnit++) {
if (boardLaneConfig[pexUnit] != SERDES_UNIT_PEX)
continue;
tmp = MV_REG_READ(PEX_CAPABILITIES_REG(pexUnit));
DEBUG_RD_REG(PEX_CAPABILITIES_REG(pexUnit), tmp );
tmp &= ~(0xf<<20);
tmp |= (0x4<<20);
MV_REG_WRITE(PEX_CAPABILITIES_REG(pexUnit),tmp);
DEBUG_WR_REG(PEX_CAPABILITIES_REG(pexUnit),tmp);
}
tmp = MV_REG_READ(SOC_CTRL_REG);
DEBUG_RD_REG(SOC_CTRL_REG, tmp);
tmp &= ~(0x03);
tmp |= 0x1<<PCIE0_ENABLE_OFFS;
if (boardLaneConfig[1] == SERDES_UNIT_PEX)
tmp |= 0x1<<PCIE1_ENABLE_OFFS;
MV_REG_WRITE(SOC_CTRL_REG, tmp);
DEBUG_WR_REG(SOC_CTRL_REG, tmp);
/*----------------------------------------*/
/* STEP - 6 PEX Only - support gen1/gen2 */
/*----------------------------------------*/
next_busno = 0;
mvOsDelay(150);
for (pexIf = 0; pexIf < 2; pexIf++) // only pexIf 0 on
{
if (boardLaneConfig[pexIf] != SERDES_UNIT_PEX)
continue;
tmp = MV_REG_READ(PEX_DBG_STATUS_REG(pexIf));
DEBUG_RD_REG(PEX_DBG_STATUS_REG(pexIf), tmp);
first_busno = next_busno;
if ((tmp & 0x7f) == 0x7E) {
next_busno++;
tempPexReg = MV_REG_READ((PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CAPABILITY_REG)));
DEBUG_RD_REG((PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CAPABILITY_REG)),tempPexReg );
tempPexReg &= (0xF);
if (tempPexReg == 0x2) {
tempReg = (MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)) & 0xF0000) >> 16;
DEBUG_RD_REG(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG),tempReg );
/* check if the link established is GEN1 */
if (tempReg == 0x1) {
mvPexLocalBusNumSet(pexIf, first_busno);
mvPexLocalDevNumSet(pexIf, 1);
DEBUG_INIT_FULL_S("PEX: pexIf ");
DEBUG_INIT_FULL_D(pexIf, 1);
DEBUG_INIT_FULL_S(", link is Gen1, checking the EP capability \n");
/* link is Gen1, check the EP capability */
addr = mvPexConfigRead(pexIf, first_busno, 0, 0, 0x34) & 0xFF;
DEBUG_INIT_FULL_C("mvPexConfigRead: return addr=0x%x", addr,4);
if (addr == 0xff) {
DEBUG_INIT_FULL_C("mvPexConfigRead: return 0xff -->PEX (%d): Detected No Link.", pexIf,1);
continue;
}
while ((mvPexConfigRead(pexIf, first_busno, 0, 0, addr) & 0xFF) != 0x10) {
addr = (mvPexConfigRead(pexIf, first_busno, 0, 0, addr) & 0xFF00) >> 8;
}
if ((mvPexConfigRead(pexIf, first_busno, 0, 0, addr + 0xC) & 0xF) >= 0x2) {
tmp = MV_REG_READ(PEX_LINK_CTRL_STATUS2_REG(pexIf));
DEBUG_RD_REG(PEX_LINK_CTRL_STATUS2_REG(pexIf),tmp );
tmp &=~(BIT0 | BIT1);
tmp |= BIT1;
MV_REG_WRITE(PEX_LINK_CTRL_STATUS2_REG(pexIf),tmp);
DEBUG_WR_REG(PEX_LINK_CTRL_STATUS2_REG(pexIf),tmp);
tmp = MV_REG_READ(PEX_CTRL_REG(pexIf));
DEBUG_RD_REG(PEX_CTRL_REG(pexIf), tmp );
tmp |= BIT10;
MV_REG_WRITE(PEX_CTRL_REG(pexIf),tmp);
DEBUG_WR_REG(PEX_CTRL_REG(pexIf),tmp);
mvOsUDelay(10000);/* We need to wait 10ms before reading the PEX_DBG_STATUS_REG in order not to read the status of the former state*/
DEBUG_INIT_FULL_S("PEX: pexIf ");
DEBUG_INIT_FULL_D(pexIf, 1);
DEBUG_INIT_FULL_S(", Link upgraded to Gen2 based on client cpabilities \n");
} else {
DEBUG_INIT_FULL_S("PEX: pexIf ");
DEBUG_INIT_FULL_D(pexIf, 1);
DEBUG_INIT_FULL_S(", remains Gen1\n");
}
}
}
/*******************************************************************************
* mvEthKW2SwitchBasicInit -
*
* DESCRIPTION: KW2 internal SW init.
* INPUT:
* ethPortNum - Ethernet port number
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthKW2SwitchBasicInit(MV_U32 enabledPorts)
{
/* MV_U32 prt;*/
/* MV_U16 reg;*/
MV_U32 ethPortNum;
MV_U32 cpuPort;
//MV_U32 enabledPorts = ((1 << 0)|(1 << 1)|(1 << 2)|(1 << 3)|(1 << 4)|(1 << 5)); //by default 0-4 are enabled
/* The 6171 needs a delay */
mvOsDelay(1000);
if (mvBoardIsInternalSwitchConnected(0))
{
ethPortNum = 0;
cpuPort = 4;
/* Force link, speed, duplex for switch port #4. */
mvEthSwitchRegWrite(0, 0x14, 0x1, 0x3E);
if (mvBoardIdGet() == MI424WR_I_ID)
/* MI424-I Specific */
/* Force link, speed, duplex for switch port #6. */
mvEthSwitchRegWrite(0, 0x16, 0x1, 0x3E);
}
else
{
//switch is connected in port 1 only
ethPortNum = 1;
cpuPort = 5;
/* Force link, speed, duplex for switch port #4. */
mvEthSwitchRegWrite(1, 0x15, 0x1, 0x3E);
if (mvBoardIdGet() == MI424WR_I_ID)
/* MI424-I Specific */
/* Force link, speed, duplex for switch port #6. */
mvEthSwitchRegWrite(0, 0x16, 0x1, 0x3E);
}
// enabledPorts |= (1 << cpuPort);
/* Init vlan of switch 1 and enable all ports */
#if 1
switchVlanInit(ethPortNum,
cpuPort,
MV_KW2_SW_MAX_PORTS_NUM,
MV_KW2_SW_PORTS_OFFSET,
enabledPorts);
#endif
/* delay only CPU port*/
/* Enable RGMII delay on Tx and Rx for port 5 switch 1 */
// mvEthSwitchRegRead (ethPortNum, MV_KW2_SW_PORTS_OFFSET + cpuPort, MV_KW2_SW_SWITCH_PHIYSICAL_CTRL_REG, ®);
// mvEthSwitchRegWrite (ethPortNum, MV_KW2_SW_PORTS_OFFSET + cpuPort, MV_KW2_SW_SWITCH_PHIYSICAL_CTRL_REG, (reg|0xC000));
#if 0
/* Power up PHYs */
for(prt=0; prt < MV_KW2_SW_MAX_PORTS_NUM; prt++)
{
if ((1 << prt) & enabledPorts)
{
/*Enable Phy power up for switch 1*/
mvEthSwitchRegWrite (ethPortNum, MV_KW2_SW_GLOBAL_2_REG_DEV_ADDR,
MV_KW2_SW_SMI_PHY_DATA, 0x3360);
mvEthSwitchRegWrite (ethPortNum, MV_KW2_SW_GLOBAL_2_REG_DEV_ADDR,
MV_KW2_SW_SMI_PHY_COMMAND, (0x9410 | (prt << 5)));
/*Make sure SMIBusy bit cleared before another SMI operation can take place*/
timeout = KW2_SW_PHY_TIMEOUT;
do {
mvEthSwitchRegRead(ethPortNum, MV_KW2_SW_GLOBAL_2_REG_DEV_ADDR,
MV_KW2_SW_SMI_PHY_COMMAND,®);
if(timeout-- == 0)
{
mvOsPrintf("mvEthPhyRegRead: SMI busy timeout\n");
return;
}
}while (reg & KW2_SW_PHY_SMI_BUSY_MASK);
mvEthSwitchRegWrite (ethPortNum, MV_KW2_SW_GLOBAL_2_REG_DEV_ADDR,
MV_KW2_SW_SMI_PHY_DATA,0x1140);
mvEthSwitchRegWrite (ethPortNum, MV_KW2_SW_GLOBAL_2_REG_DEV_ADDR,
MV_KW2_SW_SMI_PHY_COMMAND,(0x9400 | (prt << 5)));
/*Make sure SMIBusy bit cleared before another SMI operation can take place*/
timeout = KW2_SW_PHY_TIMEOUT;
do {
mvEthSwitchRegRead(ethPortNum, MV_KW2_SW_GLOBAL_2_REG_DEV_ADDR,
MV_KW2_SW_SMI_PHY_COMMAND,®);
if(timeout-- == 0)
{
mvOsPrintf("mvEthPhyRegRead: SMI busy timeout\n");
return;
}
}while (reg & KW2_SW_PHY_SMI_BUSY_MASK);
}
}
#endif
if (mvBoardIsInternalSwitchConnected(0))
{
/* Force link, speed, duplex for switch port #4. */
mvEthSwitchRegWrite(0, 0x14, 0x1, 0x3E);
}
else
{
/* Force link, speed, duplex for switch port #4. */
mvEthSwitchRegWrite(1, 0x15, 0x1, 0x3E);
}
}
/*******************************************************************************
**
** onuEponAsicFiFoReInit
** ____________________________________________________________________________
**
** DESCRIPTION: The function re-init onu EPON MAC Fifo
**
** PARAMETERS: None
**
** OUTPUTS: None
**
** RETURNS: MV_OK or error
**
*******************************************************************************/
MV_STATUS onuEponAsicFiFoReInit(void)
{
MV_STATUS status;
MV_U32 rxEnable;
MV_U32 txEnable;
/* Disable all TX */
rxEnable = 1;
txEnable = 0;
status = mvOnuEponMacOnuEnableSet(rxEnable, txEnable);
if (status != MV_OK)
{
mvPonPrint(PON_PRINT_ERROR, PON_INIT_MODULE,
"ERROR: (%s:%d) mvOnuEponMacOnuEnableSet\n\r", __FILE_DESC__, __LINE__);
return(MV_ERROR);
}
/* disable onu pon interrupt mask */
mvOnuEponMacPonInterruptMaskSet(0);
/* Turn on GMII MASK */
/* Switch TX port to Standard GE mode */
status = mvOnuEponMacTxmConfigSet(ONU_DEF_TXM_CFG_TFEC_1,
ONU_DEF_TXM_CFG_TFEC_2,
ONU_DEF_TXM_CFG_CTRL_FIFO_DIS_FCS_OFF,
ONU_DEF_TXM_CFG_MASK_GMII_ON,
ONU_DEF_TXM_CFG_BLOCK_DATA_OFF,
ONU_DEF_TXM_CFG_IPG_DONT_ADD,
ONU_DEF_TXM_CFG_MODE_GE,
ONU_DEF_TXM_CFG_ALIGNMENT_EVEN,
ONU_DEF_TXM_CFG_PRIORITY_RPRT_FIRST);
if (status != MV_OK)
{
mvPonPrint(PON_PRINT_ERROR, PON_INIT_MODULE,
"ERROR: (%s:%d) mvOnuEponMacTxmConfigSet\n\r", __FILE_DESC__, __LINE__);
return(MV_ERROR);
}
/* Enable all TX */
rxEnable = 1;
txEnable = 0xFF;
status = mvOnuEponMacOnuEnableSet(rxEnable, txEnable);
if (status != MV_OK)
{
mvPonPrint(PON_PRINT_ERROR, PON_INIT_MODULE,
"ERROR: (%s:%d) mvOnuEponMacOnuEnableSet\n\r", __FILE_DESC__, __LINE__);
return(MV_ERROR);
}
/* Wait 10ms */
mvOsDelay(10);
/* Disable all TX */
rxEnable = 1;
txEnable = 0;
status = mvOnuEponMacOnuEnableSet(rxEnable, txEnable);
if (status != MV_OK)
{
mvPonPrint(PON_PRINT_ERROR, PON_INIT_MODULE,
"ERROR: (%s:%d) mvOnuEponMacOnuEnableSet\n\r", __FILE_DESC__, __LINE__);
return(MV_ERROR);
}
/* Switch TX port to Standard EPON mode */
/* Turn off GMII MASK */
status = mvOnuEponMacTxmConfigSet(ONU_DEF_TXM_CFG_TFEC_1,
ONU_DEF_TXM_CFG_TFEC_2,
ONU_DEF_TXM_CFG_CTRL_FIFO_DIS_FCS_OFF,
ONU_DEF_TXM_CFG_MASK_GMII_OFF,
ONU_DEF_TXM_CFG_BLOCK_DATA_OFF,
ONU_DEF_TXM_CFG_IPG_DONT_ADD,
ONU_DEF_TXM_CFG_MODE_EPON,
ONU_DEF_TXM_CFG_ALIGNMENT_EVEN,
ONU_DEF_TXM_CFG_PRIORITY_RPRT_FIRST);
if (status != MV_OK)
{
mvPonPrint(PON_PRINT_ERROR, PON_INIT_MODULE,
"ERROR: (%s:%d) mvOnuEponMacTxmConfigSet\n\r", __FILE_DESC__, __LINE__);
return(MV_ERROR);
}
/* enable onu pon interrupt mask */
mvOnuEponMacPonInterruptMaskSet(0x120);
/* Enable all TX */
rxEnable = 1;
txEnable = 0xFF;
status = mvOnuEponMacOnuEnableSet(rxEnable, txEnable);
if (status != MV_OK)
{
mvPonPrint(PON_PRINT_ERROR, PON_INIT_MODULE,
"ERROR: (%s:%d) mvOnuEponMacOnuEnableSet\n\r", __FILE_DESC__, __LINE__);
return(MV_ERROR);
}
return(MV_OK);
}
/*******************************************************************************
**
** onuEponSerdesInit
** ____________________________________________________________________________
**
** DESCRIPTION: The function set serdes
**
** PARAMETERS: None
**
** OUTPUTS: None
**
** RETURNS: MV_OK or error
**
*******************************************************************************/
MV_STATUS onuEponSerdesInit(void)
{
MV_STATUS status;
MV_U32 loop = 0;
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_CLK_EN, 0x0, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_MAC_GPON_CLK_EN, 0x0, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
/* PON MAC init to GPON mode */
/* ========================= */
/* Put PON MAC to Reset */
status = asicOntMiscRegWrite(mvAsicReg_PON_MAC_SW_RESET_CTRL, 0x0, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
/* Switch to new PON MAC */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_XPON_CTRL, 0, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_CLK_SEL, 0x0, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_MAC_GPON_CLK_EN, 0x1, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_CLK_EN, 0x1, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
/* Take PON MAC out of Reset */
status = asicOntMiscRegWrite(mvAsicReg_PON_MAC_SW_RESET_CTRL, 0x1, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
/* PON MAC init to EPON mode */
/* ========================= */
/* Put PON MAC to Reset */
status = asicOntMiscRegWrite(mvAsicReg_PON_MAC_SW_RESET_CTRL, 0x0, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
/* Switch to new PON MAC */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_XPON_CTRL, 1, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_CLK_SEL, 0x0, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_MAC_GPON_CLK_EN, 0x1, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_CLK_EN, 0x1, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
/* Take PON MAC out of Reset */
status = asicOntMiscRegWrite(mvAsicReg_PON_MAC_SW_RESET_CTRL, 0x1, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
/* EPON configuration of XVR SD is done by LSP code (mvBoardEnvSpec.h, mvCtrlEnvLib.c) */
/* EPON configuration/SerDes power up and init sequence */
/* ========================================================= */
do
{
loop++;
status = onuEponSerdesPowerUpSeq();
if (status == MV_ERROR) return(status);
else if (status == MV_OK) break;
} while (loop < 10);
if (loop >= 10)
{
mvPonPrint(PON_PRINT_ERROR, PON_INIT_MODULE, "======================================\n");
mvPonPrint(PON_PRINT_ERROR, PON_INIT_MODULE, "========= Serdes Not Sync !!! ========\n");
mvPonPrint(PON_PRINT_ERROR, PON_INIT_MODULE, "======================================\n");
}
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_0_RST_TX_DOUT, 0x0, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_INTERNAL_OPEN_TX_DOOR, 0x0, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_CLK_EN, 0x0, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_CLK_SEL, 0x1, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_CLK_EN, 0x1, 0);
if (status != MV_OK)
return(status);
mvOsDelay(40);
// status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_1_BEN_IO_EN, 0x0, 0);
// if (status != MV_OK)
// return(status);
//
// mvOsDelay(10);
return(MV_OK);
}
