static void __devinit mvs_64xx_phy_hacks(struct mvs_info *mvi) { void __iomem *regs = mvi->regs; int i; mvs_phy_hacks(mvi); if (!(mvi->flags & MVF_FLAG_SOC)) { for (i = 0; i < MVS_SOC_PORTS; i++) { mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE8); mvs_write_port_vsr_data(mvi, i, 0x2F0); } } else { mw32(MVS_GBL_PORT_TYPE, 0); for (i = 0; i < mvi->chip->n_phy; i++) { mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE7); mvs_write_port_vsr_data(mvi, i, 0x90000000); mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE9); mvs_write_port_vsr_data(mvi, i, 0x50f2); mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE11); mvs_write_port_vsr_data(mvi, i, 0x0e); } } }
static void __devinit mvs_64xx_phy_hacks(struct mvs_info *mvi) { void __iomem *regs = mvi->regs; mvs_phy_hacks(mvi); if (!(mvi->flags & MVF_FLAG_SOC)) { /* TEST - for phy decoding error, adjust voltage levels */ mw32(MVS_P0_VSR_ADDR + 0, 0x8); mw32(MVS_P0_VSR_DATA + 0, 0x2F0); mw32(MVS_P0_VSR_ADDR + 8, 0x8); mw32(MVS_P0_VSR_DATA + 8, 0x2F0); mw32(MVS_P0_VSR_ADDR + 16, 0x8); mw32(MVS_P0_VSR_DATA + 16, 0x2F0); mw32(MVS_P0_VSR_ADDR + 24, 0x8); mw32(MVS_P0_VSR_DATA + 24, 0x2F0); } else { int i; /* disable auto port detection */ mw32(MVS_GBL_PORT_TYPE, 0); for (i = 0; i < mvi->chip->n_phy; i++) { mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE7); mvs_write_port_vsr_data(mvi, i, 0x90000000); mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE9); mvs_write_port_vsr_data(mvi, i, 0x50f2); mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE11); mvs_write_port_vsr_data(mvi, i, 0x0e); } } }